ModelSim Achieves Verilog Sign-off from LSI Logic

3/13/2002 - Model Technology, a Mentor Graphics company, today announced that the ModelSim® hardware description language (HDL) simulation tool has achieved Verilog, VHDL and mixed VHDL Testbench with Verilog gate-level netlist simulation sign-off from LSI Logic Corporation (NYSE:LSI). Using ModelSim, LSI Logic customers can now simulate application specific integrated circuit (ASIC) designs in VHDL, Verilog or a mix of Verilog netlist with VHDL Testbench.

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