Synopsys Accelerates VCS Performance For Verilog and Mixed-HDL Simulator

2/25/2002 - Synopsys Inc. (Nasdaq:SNPS) the technology leader for complex IC design, today announced the latest release of its industry-leading VCS(TM) Verilog simulator, VCS 6.1, and its high-performance Scirocco(TM) VHDL simulator, Scirocco 2001.10. Customer designs using these new releases show register transfer-level and gate-level simulation performance improvements of up to three times over previous versions, while also showing a reduction in memory consumption of up to 30 percent for Verilog designs. Furthermore, new cross compile technology incorporated in the 64-bit version of VCS additionally increases capacity for Verilog designs. Leveraging this technology, customers have simulated designs in excess of 20 million gates within their existing verification environments.

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