Agere Systems Tapes Out 11 Million Gate System-On-Chip

12/19/2002 - Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex integrated circuit (IC) design, announced that Agere Systems, a premier provider of communication ICs, has taped out Agere's newest SONET/SDH framer system-on-chip (SoC) using Synopsys' AstroTM physical implementation solution. The Agere MARS Universal framer IC is the industry's most integrated, full-featured and versatile framer for multi-service metro and access networks - scalable from rates of 155 megabits per second to 10 gigabits per second. The chip is comprised of 11 million gates, multiple high-speed interfaces and several hundred clock domains with a system clock speed of 155 MHz. The design was implemented in Agere's leading-edge 140 nanometer silicon process. Astro, a cornerstone product in Synopsys' complete RTL-to-GDSII solution, played a critical role in the completion of the chip by providing fast, highly efficient placement, routing and advanced physical optimizations. In addition, Astro is part of Agere's standard ASIC SoC design flow.

"Astro was vital to achieving tape out for this complex design on a tight schedule," said Jim Stefany, development director of Optical Networking Integrated Circuits at Agere. "Astro provided an excellent mix of usability and advanced capabilities, including comprehensive crosstalk prevention and correction, enabling us to efficiently close the design with correct timing, signal integrity and process rules."

For this design, Agere Systems benefited from the full scope of the complete Synopsys RTL-to-GDSII solution - the industry's most complete solution with best-in-class technology for each design phase. Agere's design flow included Synopsys' Design CompilerTM family for RTL synthesis, PrimeTime® for full-chip static timing analysis, Astro for physical implementation, Star-RCXTTM for extraction and HerculesTM for physical verification. This familiar, trusted and production-proven design tool environment was central to achieving high productivity for Agere.

"In today's environment, our customers' focus is increasingly turning to productivity where design turnaround time is at a premium," said Sanjiv Kaul, senior vice president of Corporate Applications and Marketing at Synopsys. "Agere's SoC tapeout is a great example of Astro's streamlined, easy-to-use, highly productive environment that meets designer needs for fast turnaround."

Astro is the most advanced physical implementation solution for designs at 130 nanometer and below. Astro extends the foundation of ApolloTM, Synopsys' 180 nanometer place and route solution. This common design environment, user interface and MilkywayTM database access, makes it easy for Apollo users to migrate to Astro for better performance, higher productivity, built-in signal integrity and advance process rule support. Today, Astro is in use at nine of the world's top 10 semiconductor companies.

About Synopsys
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, Calif., creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at

Synopsys and PrimeTime are registered trademarks of Synopsys, Inc., and Astro, Design Compiler, Physical Compiler, Milkyway, Hercules and Star-RCXT are trademarks of Synopsys, Inc.

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