Texas Instruments Finds Opportunity in Building Big, Fast ASICs

11/26/2002 - Texas Instruments announced its application specific integrated circuit (ASIC) team is targeting the largest and most complex products by leveraging TI's advanced semiconductor process technology, embedded intellectual property (IP), advanced packaging and design tools. The latest example, sampling with the customer now, is a 20 million gate equivalent ASIC operating at 312 MHz and containing close to 1000 signal lines. Large, high performance ASICs require a hands-on design partner like TI to successfully manufacture the chips in advanced process geometries of 130nm and below.

"The TI ASIC business is built to very closely support customers with their largest and most complex devices," said Steve Sutton, vice president of TI's ASIC business unit. "As the linkage between process technology and design becomes increasingly critical, the market is transforming from a traditional ASIC business to a complex design, co-development service with much higher levels of interaction and collaboration."

As semiconductor technology moves to more advanced process nodes and associated copper interconnects shrink to 130nm and below, ASIC customers are having to consider challenges that did not appear on designs implemented in older technologies. For example, device packaging must be considered early on because of its effect on I/O performance and signal integrity. The latest TI design includes a custom TI flip-chip package that enables the design to meet the customer's required performance levels. Timing closure, test methodology and layout are also more closely affected by the manufacturing process and OEMs are finding it easier to hand these concerns over to their ASIC supplier rather than dealing with them in-house.

"There continues to be a thriving ASIC market for the few companies that can build these large, highly complex products where the old methodology of designing it and then throwing it over the wall to manufacturing no longer works," said Jerry Worchel, senior analyst, In-Stat/MDR. "With a wide variety of high quality IP, systems expertise and leading-edge process technology, TI is one of the companies well suited to serve this segment."

The high-performance requirements for network infrastructure products require TI's expertise in high-speed serial and parallel I/O. The latest design is a data traffic manager that utilizes multiple high-speed DDR parallel busses to transmit up to 800 megabits per second per pin. TI's high density SRAM also contributed to the success of this ASIC design.

A critical advantage in delivering leading-edge silicon is TI's use of its hierarchical ASIC design flow to efficiently partition the design into blocks across the entire design team, enabling concurrent design at the RTL and physical design abstraction. TI's hierarchical methodology uses advanced tools from EDA vendors and TI that are tightly integrated to provide a complete flow, from design partitioning and timing closure, to signal integrity and test vectors. On-chip test is also offered with TI's latest design, including Memory BIST to validate memory, Full SCAN is implemented via ATPG to insure logic operation and JTAG is available to perform I/O test. The new ASIC is manufactured using TI's 130-nanometer process and is now sampling at the customer.

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