11/20/2002 - Cadence Design Systems, the world's leading supplier of electronic design products and services, announced physical synthesis customers NEC and AMCC have adopted Cadence® NanoRoute(TM) Ultra nanometer router for routing-based timing and signal integrity (SI) closure for leading-edge 130- and 90-nanometer SoC design. A key technology of the Cadence Encounter(TM) system, NanoRoute Ultra delivers optimized wires with simultaneous timing and SI closure for flat and hierarchical multi-million gate designs.
Nanometer design implementation requires explicit wire information for timing and SI closure; current physical synthesis and optimization techniques that depend solely on placement and estimated routing are no longer sufficient. Physical wire dynamics, such as wire topology, layer selection, track assignments, and cross-coupling can cause final timing results to differ by as much as 700 percent from placement-based predictions. NanoRoute Ultra picks up where physical synthesis leaves off, by completing the timing and SI optimization concurrently during routing, when actual wire information is available.
"Developing high-end VLSI chips using the most advanced process geometries has forced us to rethink how, when, and where in the design cycle we account for signal integrity effects in order to achieve timing and design closure," said Hiroshi Ichiryu, Sr. Manager, CAD Engineering Department, Computers Division, NEC Corporation. "NanoRoute Ultra has equipped us with the necessary tools to navigate these issues completely in routing and is a necessary complement to our existing design tools."
"NanoRoute Ultra has repeatedly demonstrated its ability to quickly achieve clean routing on our most advanced ASIC design platforms, the CB-130 and CB-90, built on 130-nanometer and 90-nanometer process technologies respectively," said John Fallin, general manager, Design Solutions Center, NEC Electronics America, Inc. "We've had to establish an advanced design closure methodology, and NanoRoute is one of the key components of this solution."
"NanoRoute Ultra delivers the speed and capacity necessary for routing in addition to providing exceptional rectification of signal integrity, timing and antenna issues typical of our advanced process designs," said George Serhan, VLSI director, AMCC's Switching and Network Processing Division. "We have successfully taped-out using NanoRoute in tandem with our existing physical optimization solution with further developments currently underway. Together, AMCC and Cadence have been successful in deploying this new and groundbreaking technology."
About NanoRoute Ultra
NanoRoute Ultra is the electronic design industry's first unified routing and wire-centric physical optimization solution. NanoRoute Ultra performs detailed routing concurrently with on-the-fly incremental extraction, timing analysis, and SI avoidance and fixing to provide designers with a robust wires-centric design closure solution. This approach slashes nanometer design cycle times by reducing front-to-back iterations between physical synthesis and final implementation.
Patent-pending graph-based routing algorithm from Cadence combines the flexibility of chip-level routing with the performance and capacity to handle in excess of 10-million gates flat and 100-million gates hierarchically. NanoRoute Ultra also supports complete power planning and routing, clock routing, wire editing, physical verification, sign-off static timing analysis, chip finishing, and 90 nanometer design rule support. It also includes the unified Cadence Encounter system design cockpit and database for a consistent user interface and in-system memory model from RTL to GDSII.
"NanoRoute Ultra features superior routing technology that delivers the best wires for our customers' nanometer designs," said Ping Chao, senior vice president and general manager, Digital IC Solutions at Cadence. "As part of the Cadence Encounter system or as a standalone complement to a third-party physical optimization or physical synthesis-based digital design flow, NanoRoute Ultra helps our customers create optimal wires for first silicon success."
Pricing and Availability
Available in December 2002, Cadence NanoRoute Ultra will be native to Encounter system RTL-to-GDSII product configurations-SoC Encounter(TM) and Nano Encounter-and sold standalone as NanoRoute Ultra. The list price for NanoRoute Ultra standalone is $275,000 U.S. For information about upgrade paths for customers or for international pricing, please contact a local Cadence office.
Cadence is the world's largest supplier of electronic design technologies and services. Leading computer, networking, wireless, and consumer electronics companies use the company's solutions to design electronic systems and semiconductors down to nanometer scale. IEEE, the world's largest technical professional society, honored Cadence with its 2002 Corporate Innovation Recognition award. With approximately 5,600 employees and 2001 revenues of approximately $1.4 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN.
Previous Page | News by Category | News Search
If you found this page useful, bookmark and share it on: