11/20/2002 - Taiwan Semiconductor Manufacturing Company, the leader in semiconductor foundry technology, and Cadence Design Systems, the world's leading supplier of electronic design products and services announced an engineering collaboration milestone being achieved in addressing signal integrity (SI) issues in 130-nanometer (nm) and 90 nm process technologies. As a result, TSMC has qualified the Cadence tool suite to be included in the next generation TSMC Reference Flow.
"TSMC's expertise in developing design methodology for advanced silicon technologies coupled with Cadence's design automation strength is a powerful combination," said Genda Hu, vice president of Corporate Marketing at TSMC. "We are pleased that our collaboration with Cadence to develop TSMC Reference Flow 4.0 has made significant progress. The integration, performance, and capacity of Cadence SoC Encounter system have been proven with real nanometer circuit design examples. We anticipate this Reference Flow 4.0 will enable our customers to greatly shorten the design cycle and to maximize first-pass silicon successes when using TSMC's advanced technologies."
"A close relationship between our foundry and our design technology partner is an important factor for our success at 130 nm and below," said Greg Buchner, vice president of engineering at ATI Technologies, Inc. "We are very pleased to see TSMC and Cadence collaborate closely on key issues such as signal integrity closure."
TSMC's Reference Flow 4.0 will incorporate the Cadence Encounter system from virtual prototyping to physical implementation. This complete system enables designers to account for signal-integrity effects early in the design process, and to make systematic, predictable progress toward signal-integrity sign-off.
"TSMC continues to develop and provide its customers with advanced design methodologies to better utilize its industry leading process technologies," said Charlie Huang, corporate vice president of Business Development at Cadence. "We are very happy to further strengthen and enhance our partnership with TSMC, and collaboratively solve difficult nanometer design challenges such as full-chip signal integrity and timing closure. We look forward to continued collaboration in the future."
TSMC is the world's largest dedicated semiconductor foundry, providing the industry's leading process technology and the foundry industry's largest portfolio of process-proven library, IP, design tools and reference flows. The company operates two advanced 300mm wafer fabs, seven eight-inch fabs and two six-inch wafer fabs. TSMC also has substantial capacity commitments at two joint ventures fabs (Vanguard and SSMC) and at its wholly-owned subsidiary, WaferTech. In early 2001, TSMC became the first IC manufacturer to announce a 90-nanometer-micron technology alignment program with its customers. TSMC's corporate headquarters are in Hsin-Chu, Taiwan.
Cadence is the world's largest supplier of electronic design technologies and services. Leading computer, networking, wireless, and consumer electronics companies use the company's solutions to design electronic systems and semiconductors down to nanometer scale. IEEE, the world's largest technical professional society, honored Cadence with its 2002 Corporate Innovation Recognition award. With approximately 5,600 employees and 2001 revenues of approximately $1.4 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN.
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