Fujitsu Deploys Cadence Nanometer Analysis Technology to Achieve Timing Closure for High-end Asic Designs

11/20/2002 - Cadence Design Systems, the world's leading supplier of electronic design products and services, and Fujitsu announced that Fujitsu has deployed Cadence® VoltageStorm(TM) and SignalStorm(TM) as the standard power verification and nanometer delay calculation solutions for its high-end application-specific integrated circuits (ASICs).

By adopting this Cadence technology, Fujitsu believes that it will be able to dramatically increase the accuracy of its timing verification and speed timing closure for high-end, 130 and 90 nanometer ASIC and ASSP designs targeting applications such as networking, digital home electronics, and information technology.

"It is very difficult, time-consuming, demanding work to conduct verification and analysis for high-end ASIC development at 130 nanometer process technology - and this will only become more difficult for 90 nanometer technologies," said H. Takaoka, director, Physical Design CAD Dept., Technology Development Div., Fujitsu Limited. "By making Cadence SignalStorm and VoltageStorm a standard part of our design flow, we will be able to account for signal-integrity effects on path delay, resulting in highly accurate timing verification and faster timing closure - even for our largest designs."

For today's large-scale, system-on-chip (SoC) designs, designers must consider physical phenomena which were not issues in smaller-scale designs. As process geometries continue to decrease in size, highly accurate nanometer delay calculation that accounts for complex net parasitics, and signal integrity issues such as voltage (IR) drop on delay, has become indispensable.

The combination of VoltageStorm and SignalStorm provides designers with a solution to the ever-present and difficult-to-analyze signal integrity timing issues of nanometer-scale design. VoltageStorm, the de facto standard for full-chip power grid verification, quickly provides accurate, instance-based IR drop data to SignalStorm, which uses this data to provide nanometer delay calculation that is accurate to within 2 percent of SPICE.

Because SignalStorm's delay calculator is so accurate and because it is also 4-20 times faster than conventional delay calculators, Fujitsu expects to verify ASICs and SoCs four times larger with undiminished turnaround time. Fujitsu has already incorporated VoltageStorm and SignalStorm into its design flow and plan to apply the tools to production design work.

"Signal integrity timing effects, including the impact of IR drop on timing, are a critical issue for our customers as they struggle to achieve timing closure for large ASICs and SoCs targeted to nanometer-scale technologies," said Jim Bailey, general manager at Cadence. "Leading companies such as Fujitsu understand that nanometer delay calculation for nanometer designs must consider all of these factors. We are very pleased to work with Fujitsu to deploy SignalStorm and VoltageStorm to address this pivotal issue for their advanced ASIC designs."

About Cadence
Cadence is the world's largest supplier of electronic design technologies and services. Leading computer, networking, wireless, and consumer electronics companies use the company's solutions to design electronic systems and semiconductors down to nanometer scale. IEEE, the world's largest technical professional society, honored Cadence with its 2002 Corporate Innovation Recognition award. With approximately 5,600 employees and 2001 revenues of approximately $1.4 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN.

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