11/19/2002 - Artisan Components, a leading provider of semiconductor intellectual property (IP), and Cadence Design Systems, the world's leading supplier of electronic design products and services, announced a five year agreement to jointly develop tightly integrated systems, including IP libraries, design technology, and semiconductor process data, to manage the risks of nanometer design. The first result of the collaboration is a system to address signal-integrity, a critical risk factor for nanometer designs. This system enables customers to address signal-integrity early in the design process, and establish a predictable path to signal-integrity sign-off.
"Investment in a new system that includes tools, flows, libraries, and silicon feedback is required to address nanometer design issues," said Mark Templeton, president and CEO of Artisan. "Our goal is to establish long-term collaboration efforts with key industry leaders such as Cadence to provide up-to-the-minute design solutions for our customers."
"The challenges our customers face with nanometer design can only be met with a new, integrated approach to both technology and partnerships," said Penny Herscher, executive vice president and chief marketing officer at Cadence. "Cadence is investing in critical relationships with the leading suppliers such as Artisan to ensure our customers are successful. By enabling our customers to manage design risk, we are supporting the growth of the pure-play foundry model that is critical to so many of our customers."
"We postulated two years ago that the key to nanometer design success would be 'next-generation' collaboration. We have already seen success on the silicon side of the equation. It is heartening to see collaborative behaviour taking root on the design side," said Genda Hu, vice president, corporate marketing, Taiwan Semiconductor Manufacturing Company.
Nanometer Design Requires a Wires-First Approach
In nanometer design, ever-thinner wires are packed tightly together, producing unintended electrical effects that impair signal integrity. These wire-centric signal-integrity effects can be addressed accurately only after routing. Design teams need full-chip detailed design implementation -including detailed routing-the first day of implementation and every day thereafter. This wires-first approach, offered in Cadence Encounter® design system, enables design teams to account for signal-integrity effects early in the design process, and to make systematic, predictable progress toward signal-integrity sign-off.
Artisan will extend the models for its industry-leading standard cell and memory libraries to include the detailed characterization data required for the Cadence signal-integrity solution. Artisan will use large-scale deployment of Cadence Spectre® Circuit Simulator to more quickly, efficiently and accurately recharacterize its libraries with each new set of process rules, ensuring continuously up-to-the-minute models.
Customers will use the signal-integrity library views provided by Artisan as part of the Cadence Encounter flow to assess signal-integrity issues accurately throughout their design process. The Cadence Encounter continuous convergence methodology leads to signal-integrity sign-off using the Cadence CeltIC(TM), SignalStorm(TM) and VoltageStorm(TM) products.
"We are pleased that two of our top suppliers, Artisan and Cadence, are working closely to address the most difficult engineering issue we face today: risk of first tape out failure due to nanometer signal-integrity effects," said Pantas Sutardja, CTO of Marvell Semiconductor. "I look forward to the integrated design capabilities from these two industry leaders."
"For our customers to be successful on first silicon at 130 nm and below, they need updated, detailed models and a system of libraries, design technology and methodologies to apply that silicon-based knowledge," said John Goodenough, global design methodology manager at ARM. "We are pleased to see supply-chain leaders such as Artisan and Cadence collaborating to supply such a system to address the crucial issue of signal-integrity sign-off."
Signal-integrity sign-off library views for use with the Cadence Encounter design system are available now from Artisan upon customer request for their choice of a variety of pure-play foundries.
About Artisan Components
Artisan Components, Inc. is a leading semiconductor intellectual property (IP) provider. The company's design platforms are licensed to over 1000 companies worldwide. Artisan's design platforms provide IC designers with a common interface to a range of process technologies from the world's leading foundries. Built on Artisan's Process-Perfect™ memory generators, standard cell and I/O libraries, Artisan's design platforms include a comprehensive set of views and models supporting leading design tools and methodologies. Artisan's worldwide network of EDA, IP and design service partners extend the Artisan standard to a complete set of system level design and integration solutions. Artisan is headquartered in Sunnyvale, California and its stock is traded on the Nasdaq Stock Exchange under the symbol ARTI.
Cadence is the world's largest supplier of electronic design technologies and services. Leading computer, networking, wireless, and consumer electronics companies use the company's solutions to design electronic systems and semiconductors down to nanometer scale. IEEE, the world's largest technical professional society, honored Cadence with its 2002 Corporate Innovation Recognition award. With approximately 5,600 employees and 2001 revenues of approximately $1.4 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN.
Previous Page | News by Category | News Search
If you found this page useful, bookmark and share it on: