11/14/2002 - 0-In Design Automation, The Assertion-Based Verification Company, announced the availability of CheckerWare® monitors for the AGP 8x, HyperTransportTM, InfiniBandTM and RapidIOTM standards. Leading integrated circuit (IC) design teams and ABV users can increase verification productivity by utilizing these pre-verified Verilog register transfer level (RTL) monitors to validate compliance with the latest protocol and interface standards.
CheckerWare monitors are developed with leading customers as part of 0-Inís continuing commitment to promote industry standards through the support of open standards. The unique capabilities of 0-In monitors include formal tool support, testbench and simulator independence, and interoperability with all tools in existing verification environments. Using 0-Inís CheckerWare monitors, designers eliminate the time spent on developing and debugging protocol monitors and are free to devote more time to design and verification.
"System-on-chip companies need to increase verification productivity and reduce their time-to-market," said Emil Girczyc, 0-In president and CEO. "0-In is dedicated to providing customers with a comprehensive ABV solution. Our CheckerWare library and monitors are key to providing a methodology designers can use with their existing simulation, formal verification, hardware acceleration and emulation tools."
"By leveraging 0-In's standards expertise and utilizing CheckerWare monitors, our design verification teams are able to focus on design validation, resulting in a more thorough design verification" said Jonathan Sun, design manager at Sun Microsystems, Inc.
Designers can reduce the effort required to verify their designs by using the extensive CheckerWare library and suite of over 20 monitors. CheckerWare monitors certify that the designs conform to interface standards and enable products to be interoperable with all products that support these standards. During simulation, CheckerWare monitors warn users of any protocol violations and generate structural coverage statistics to measure testbench efficacy. The same monitors serve as targets and constraints to guide formal verification tools, including the 0-In Search dynamic formal verification tool.
The AGP 8x, HyperTransport, InfiniBand and RapidIO monitors are the latest interface models to emerge from the 0-In development pipeline; PCI ExpressTM and Serial-Attached SCSI monitors are among the next group of models also to be delivered this quarter.
"0-In's HyperTransport monitor is designed to enable our members to thoroughly verify that their designs conform to the HyperTransport I/O Link specification," stated Gabriele Sartori, president of the HyperTransport Technology Consortium. "Leading companies that are developing networking, telecommunications and processor ICs with the HyperTransport technology can use 0-In's verification infrastructure to help more efficiently validate their implementation."
The growing 0-In CheckerWare monitor suite -- including PCI, PCI-X, AMBA, AGP, SPI-4.2, POS-PHY, UTOPIA, HyperTransport, InfiniBand, RapidIO, SDRAM and DDR SDRAM -- is now available to design teams.
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif.
0-In® and CheckerWare® are registered trademarks of 0-In Design Automation, Inc.
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