11/6/2002 - Leading EDA vendors Mentor Graphics, Synopsys, and Synplicity have announced full support for Altera's new StratixTM GX device family.
"Together with our EDA partners, Altera is able to provide a seamless system-on-a-programmable-chip (SOPC) design flow that maximizes performance of the high-speed transceivers in our Stratix GX devices and allows designers to focus on board-level issues rather than development tool interoperability," said Tim Southgate, Altera's vice president of software and tools marketing.
The new block-based design algorithms in the Quartus® II version 2.1 design software, combined with advanced inference and optimization technology, allow SOPC designers to easily utilize the 3.125 Gbps transceivers, DSP block, TriMatrixTM memory, and MultiTrackTM interconnect features of the Stratix GX device family.
"Our industry-leading FPGA design solutions are tightly integrated with Altera's Quartus II design flow, providing a comprehensive design and verification platform for system-level engineers," said Simon Bloch, general manager of the Mentor Graphics HDL and FPGA design division. "Through Mentor's support for Altera's LogicLockTM design methodology, designers are now able to integrate system-level building blocks, including multi-gigabit transceivers available in Stratix GX devices, in an incremental manner without compromising design performance."
OEM versions of the Mentor Graphics LeonardoSpectrumTM synthesis software (version 2002e) and ModelSim (version 5.6a) simulation software are included as part of the standard package in Altera's software subscription program.
"Synopsys specializes in providing designers with an ASIC-like flow for high-performance programmable logic devices (PLDs)," said Michael Jackson, vice-president and general manager of FPGA Synthesis at Synopsys. "With the increasing system-level functionality available in leading-edge FPGA devices such as Stratix GX, our FPGA CompilerTM II is able to deliver Block-Level Incremental Synthesis (BLIS) which automates the hierarchy management for Altera's LogicLockTM design methodology and enables reduced design cycles for our customers."
"We are pleased to provide our mutual customers with timely support for Altera's new Stratix GX device family," said Jeff Garrison, director of FPGA products at Synplicity. "We leveraged our extensive synthesis expertise in mapping to complex programmable logic architectures in order to support these devices. Besides supporting complex DSP and memory blocks in the Stratix GX devices, our market-leading Synplify® and Synplify Pro® synthesis tools provide a seamless flow for designs that instantiate the high-performance gigabit transceivers in the RTL code, enabling our customers to obtain better performance and area utilization for the Stratix GX devices."
Pricing and Availability
The Stratix GX device family is supported by Mentor Graphics LeonardoSpectrum version 2002e and ModelSim version 5.6a, Synplicity Synplify version 7.2, and Synopsys FPGA Compiler II version 3.8. Quartus II version 2.1 design software is now available to all customers on active subscription. The annual subscription for the Altera design software is $2,000 for a node-locked PC license, which includes full-featured Quartus II and MAX+PLUS® II design software, OEM synthesis tools from Mentor Graphics, OEM simulation tools from Model Technology, and 12 months of software upgrades. New or existing customers may obtain a software subscription at the Programmable eStore on the Altera web site or from Altera distributors worldwide.
About Stratix GX FPGAs
The Stratix GX family is Altera's second-generation embedded transceiver family based on a 0.13-Ám process technology with 1.5-V core voltage. Stratix GX devices have up to 20 embedded 3.125-Gbps transceivers and up to 45 differential I/O pins with dedicated dynamic phase alignment (DPA) capability supporting up to 1-Gbps source-synchronous data transfers. Stratix GX devices also offer up to 41,250 logic elements (LEs), 3.27 Mbits of TriMatrixTM memory, 14 DSP blocks, eight phase locked loops (PLLs), TerminatorTM technology for impedance matching and signal integrity and advanced I/O buffers capable of interfacing with high-speed memory devices such as DDR SDRAM, QDR SRAM, QDR II SRAM, ZBT SRAM, DDR FCRAM and SDR SRAM devices.
Altera Corporation (NASDAQ: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide.
Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. Arm is a registered trademark of ARM Limited. LeonardoSpectrum is a trademark of Mentor Graphics Corporation. Synplify and Synplify Pro are registered trademarks of Synplicity, Inc.
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