Xilinx Extends Leadership in FEC Technology with Turbo Products Code Cores for FPGAs

11/4/2002 - Xilinx announced the industry's fastest commercially available, Turbo Product Code (TPC) encoder and decoder Forward Error Correction (FEC) cores. The new cores are fully compatible with Comtech AHA Corporation's TPC devices and make it easy for system engineers to adopt advanced TPC forward error correction technology today. Additionally, Xilinx also announced the availability of an Additive White Gaussian Noise (AWGN) core designed to assist engineers in accurately measuring the bit error rate (BER) performance of communication systems.

"At high codes rates, TPC error correction performance approaches closer to the theoretical Shannon Channel Capacity Limit than any other commercially available error correction codes. The TPC's increased coding gain allows system engineers to reduce transmission power, increase transmitted data rates and transmission distance, or reduce antenna size," said Bill Thomson, president of Comtech AHA.

The cores support the fixed broadband wireless access standards (IEEE802.16 LMDS and MMDS) and provide a data rate of over 155Mbps. The TPC cores also provide latencies less than 10 microseconds (critical in meeting the MMDS specifications), and a coding gain greater than 10dB at 10E-6 BER compared to legacy Viterbi/ReedSolomon FEC when used in a MMDS faded channel. In addition to MMDS/LMDS applications, this high coding gain makes the TPC core an ideal choice for spectrally efficient, high data rate, military communications links. The new TPC encoder/decoder cores are part of an extensive library of pre-verified Xilinx DSP algorithms which includes FFTs, filters, digital down converters that can be implemented in the Virtex-IITM Series FPGA logic fabric using resources such as 556 embedded 18x18 multipliers, logic cells and up to 10 Mbits of on-chip memory.

"Xilinx leverages Comtech AHA's leadership position in the FEC field to bring a proven product to market that has been tested in thousands of communication links around the world," said David Squires, director of the DSP Center of Excellence at Xilinx. "In addition, this collaboration provides our customers with a migration path to Comtech AHA ASIC solutions, providing the lowest possible cost for extremely high volume applications. And the performance of the TPC cores demonstrates that the Virtex-II and Virtex-II Pro FPGAs are world-class DSP engines."

Price and Availability
The new cores are available immediately and downloadable over the web. The TPC encoder (source code), the TPC decoder (fixed netlist) and the AWGN (source code) cores are priced at $1,000, $20,000 and $1,000 respectively.

Xilinx XtremeDSP Initiative
The Xilinx XtremeDSP initiative introduced in 2000, driven by the broadband revolution, addresses the increasing need for high-performance DSP solutions. The initiative represents a major commitment by Xilinx to further establish its leadership as a high-performance DSP solutions provider. The Xilinx DSP solution comprises unique DSP features in its Virtex-II series FPGAs such as up to 556 embedded 18x18 multipliers, over 10 megabits block and distributed memory, pre-engineered DSP algorithms, system-level DSP development tools, and a rapidly growing network of Xilinx AllianceCORETM and XPERT partners who provide DSP intellectual property cores and design services.

About Xilinx
Xilinx, Inc. (NASDAQ: XLNX) is the worldwide leader of programmable logic and programmable system solutions.

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