10/22/2002 - Long known as a leader in the embedded memory market, Virage Logic, is extending that role to the broader category of semiconductor Intellectual Property (IP) platforms by announcing its first foray into logic components. With its new family of Area, Speed and Power (ASAP) LogicTM products, which includes the ASAP High-Speed (HS) Metal Programmable Cell Library and the ASAP High-Density (HD) Standard Cell Library, Virage Logic is slashing not only the price and power consumption of the overall chip, it is also improving performance.
Targeted at high growth markets such as consumer, communications and networking, graphics, and portable and handheld devices, the new ASAP Logic products typically deliver over a 20 percent increase in logic block area utilization. Silicon proven on a variety of process geometries (0.25um, 0.18um, 0.13um) at leading integrated device manufacturers (IDMs), the ASAP Logic product line is being first introduced to fabless semiconductor customers on TSMC's 0.13-micron logic process.
"Yamaha's high volume digital audio applications are based on designs that are quite area-sensitive," said Yukichi Ono, senior engineer, Semiconductor Division, Yamaha Corporation. "Our first experience with Virage Logic's ASAP Logic architecture resulted in around 20 percent reduction in area. With these dramatic results, we have decided to standardize on Virage Logic's ASAP Logic for many Yamaha designs."
The underlying architecture provides the same performance with shorter cell sizes as compared to competitive standard cells. Through its patented routing and cell architecture, the ASAP Logic products are ideally suited for deep sub-micron applications where optimized routability and minimized power consumption are key.
"Because we believe that highly reliable System-on-Chip (SoC) designs require specialized components in order to meet demanding specifications and time-to-market pressures, we are delivering application-optimized semiconductor IP platforms that are built on advanced technology in both the memory and logic arenas," said Adam Kablanian, CEO and president, Virage Logic. "We were the first to introduce both a self-testable and repairable embedded memory, as well as a non-volatile embedded memory that is manufacturable in a standard CMOS logic process. Now, we are the first to introduce commercially available metal programmable cell libraries that enable significant mask cost reduction for 130- and 90-nanometer (nm) process geometries."
ASAP HS Metal Programmable Cell Library
With the ASAP HS Metal Programmable Cell Library, Virage Logic has overcome a key barrier to low- and medium-volume SoC implementation — high mask costs — without causing any performance degradation. Because of its advances in pin accessibility and power routing, the HS Metal Programmable Cells provide similar area and performance as commercially available conventional standard cells without the penalty of all-layer costs. If a revision is needed, the designer only has to redesign the block, a few metal and via masks, thereby saving hundreds of thousands of dollars by preserving all other masks.
ASAP HD Standard Cell Library
In order to reduce the overall cost of silicon, Virage Logic's ASAP HD Standard Cell Library leverages the ASAP Logic superior place-and-route and cell architecture that is ideal for larger numbers of metal layers. Additionally, the architecture provides significantly increased pin accessibility and eliminates cell placement blockage from the power grid. The standard cells deliver, at minimum, a 20 percent logic block area savings compared to any conventional standard cell architecture. Depending upon the overall chip architecture, this may result in a 10 percent reduction in overall chip size and cost, making it ideal for high volume applications such as consumer products. For most applications, a 10 percent cost savings can double chip profitability. For example, in a 130-nm logic process, a 10 percent savings for one million units can represent a dollar savings of $1 million to $10 million, depending on chip size.
Availability and Pricing
The ASAP HS Metal Programmable Cell Library licensing fee starts at $50,000 (U.S. list price) per design, and the ASAP HD Standard Cell Library licensing fee starts at $25,000 (U.S. list price) per design for fabless customers. Both products are available now on TSMC's 0.13-micron standard logic process.
About Virage Logic
Virage Logic (Nasdaq: VIRL) is a global leader in application optimized semiconductor IP platforms based on memory, logic and design tools that are silicon proven and production ready. Virage Logic meets market demands of cost reduction, while improving performance and reliability for fabless and integrated device manufacturer (IDM) companies focused on the consumer, communications and networking, handheld and portable, and graphics markets.
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