Teradiant to Reveal Architecture of First Configurable 10Gbps to 40Gbps Network Processing Chipset

10/16/2002 - Teradiant Networks, a leading developer of silicon solutions for next-generation networks, will reveal the architecture and detailed specifications of the industry's first 40Gbps network processing engine, at Network Processors Conference West. The TeraPacketTM chipset consists of semiconductors that handle packet processing and traffic management on Internet routers and multiservice switches in edge and core networks. TeraPacket will supercede the bandwidth and performance of today's network processors and NPUs while providing industry-leading low power, cost and consumed space. TeraPacket chipsets come in three versions - 10Gbps, 20Gbps, and 40Gbps - each consisting of one multiservice packet engine and one multiservice traffic manager.

Each TeraPacket chipset is fully configurable, providing guaranteed deterministic wire-speed performance on line cards designed for gigabit Ethernet, 10gigabit Ethernet, OC48, OC192 and OC768 aggregate throughput. For router and switch developers, this performance means that guaranteed 10Gbps, 20Gbps or 40Gbps throughput is available on a single line card, under any network traffic conditions and with all chip functions enabled. By contrast, today's programmable network processors are inherently not deterministic, meaning that achieving 40Gbps performance with programmable chips may require up to four line cards. TeraPacket's integration of components and an innovative shared-memory design provide major reductions in power consumption and line card cost, when compared with traditional network processor architectures.

The architecture of Teradiant's configurable network processing engines also means that no micro-code development is required. "The use of high-level APIs enabled Teradiant's control-plane team to incorporate our routing and switching software in a short period of time," added Steve Mock, VP of Business Development for IP Infusion, a leading provider of intelligent network software for enhanced IP services.

To facilitate development of line cards based on the TeraPacket chipset, Teradiant has partnered with leading vendors of other standard line card components. These include framers, security co-processors, network search engines, SRAMs, packet memory, CPUs, switch fabric, FPGAs, and related line-card components. Partners include IBM, IDT, IP Infusion, PetaSwitch, PMC-Sierra, TAU Networks, and TeraCross. All of Teradiant's interfaces are published, industry-standard interfaces.

"Teradiant's ability to achieve deterministic 40Gbps performance on a single line card is unprecedented, and results in part from its success in seamlessly interfacing TeraPacket to our 256Kx36 IP co-processor, which provides industry-leading performance of more than 100 million searches per second," said Ben Chang, strategic marketing manager for IDT's IP co-processor division. "As the leading supplier of network search engines, we look to work with companies that share our vision to provide best-of-breed solutions for our mutual customers."

Conference attendees can view a TeraPacket architecture presentation on Wednesday, October 23, 2002, at 4:15pm in the San Jose Convention Center. Attendees who visit Teradiant's booth (#306) at the convention center October 23-24 can view live data on a network carrying IP and MPLS traffic. Teradiant will also demonstrate a web-based simulator called CASE that enables users to obtain cycle-accurate views of actual system performance at wire speeds.

Previous Page | News by Category | News Search

If you found this page useful, bookmark and share it on: