10/16/2002 - Xilinx announced the availability of ModelSim® Xilinx® Edition II (MXE II) tool version 5.6a. This new version of MXE II supports new hierarchical netlist capabilities offered exclusively by Xilinx, and new productivity features of the ModelSim simulation environment. The exclusive hierarchical netlist feature allows engineers to shorten their design cycle by simplifying the time consuming process of correlating timing simulation results with the original RTL source code during design debug.
Incremental compile saves verification time
ModelSim and Xilinx hierarchical netlist generation also work in concert with Xilinx exclusive incremental design, enabling verification engineers to focus their efforts only on areas of a design that have changed. Preserving the placement and routing of unchanged portions also guarantees the performance of those blocks. This means customers using an incremental design flow can focus their design debug efforts on areas of the design that have changed as a result of design revisions.
"Improving the debug cycle time is a constant driver for product development at Model Technology," said John Lenyo, director of marketing, Model TechnologyTM, a Mentor Graphics company. "Combining Xilinx's incremental design and hierarchical netlist features with ModelSim's industry-leading simulation debug capabilities will enable designers to significantly reduce the time it takes to find and fix problems."
ModelSim productivity enhancements
MXE II enhances designer productivity by including a variety of new features that accelerate design verification when using MXE II:
Price, Delivery and Availability
Pricing for ModelSim XE II starts at $945 for an annual license and includes the first year of maintenance and support. ModelSim XE II is also available in a bundled configuration that includes design entry, synthesis, simulation and implementation tools for only $1295 from Xilinx E-business website. MXE II is available for download from the Xilinx Web site. Model Technology offers upgrade paths from MXE II to ModelSim PE or ModelSim SE, enabling Xilinx customer to leverage their knowledge of the ModelSim simulator in environments which support faster simulation for higher density designs.
About Xilinx ISE version 5.1i
With ISE 5.1i, Xilinx is delivering "ASIC-strength" design tools to exploit the power of Virtex-II Pro silicon, ranging in device densities from 40,000 to more than eight million system gates. Designers are benefiting from a 2X improvement in compile times (an increase from 100,000 to 200,000 gate/min) and a 40 percent gain in device speeds over last year's software release. With an installed base of more than 150,000 design seats, and more than 50 percent market share in the PLD industry, Xilinx ISE is widely regarded as the de facto standard methodology for programmable logic design. ISE supports the design, synthesis, implementation, and verification of all Xilinx leading programmable logic devices, including Spartan®-II, Spartan-IIE, Virtex®, Virtex-E, Virtex-IITM, Virtex-II ProTM, and all CoolRunner® series devices.
Xilinx, Inc. (NASDAQ: XLNX) is the worldwide leader of programmable logic and programmable system solutions.
Mentor Graphics and ModelSim are registered trademarks and Model Technology is a trademark of Mentor Graphics Corporation.
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