10/15/2002 - Cypress Semiconductor introduced Vichara 81000, the industry’s first Search Supervisory Coprocessor. The Vichara coprocessor enables packet processors to achieve 40 Gbps throughput by offloading search-intensive processing and managing multiple searches. It maximizes look-aside (LA-1) bus bandwidth and simplifies overall search-system management. When used in conjunction with Cypress’s AyamaTM NSE10000 family of network search engines (NSEs), the Vichara 81000 enables as many as 266 million searches per second (MSPS).
The Vichara 81000 relieves network processors (NPUs) and application specific integrated circuits (ASICs) of routing lookups and policy-resolution functions. By offloading these search-related instructions, the Vichara 81000 increases the packet processor’s ability to perform other linecard functions, resulting in more processor headroom. It also relieves packet processors of control-function management by providing direct connectivity and hardware features to perform out-of-band control updates for policing and aging functions, enabling the NPU/ASIC to process more packets per second at the same wirespeed.
"Complexity of the linecard search subsystem is increasing with the advent of services such as quality of service (QoS), policy and billing," said Jag Bolaria, senior analyst at the Linley Group and co-author of A Guide to Classification and Traffic Management Coprocessors. "All of these advanced features involve multiple lookups per packet, varied searches and the sharing of databases by multiple processors. At 2.5 Gbps and beyond, packet processors are struggling to maintain throughput and meet the requirements for these services. Cypress is the first to address this problem using its search supervisory coprocessor. The Vichara coprocessor offloads search instructions and data from the packet processors to minimize the search complexity while providing significant processing headroom. There's no other product on the market today that has solved this issue so elegantly."
"The increasingly complex nature of policy- and forwarding-based searches has created an urgent need for a highly intelligent solution to manage and coordinate searches in a subsystem that could contain multiple processors, NSEs and memory," said Christopher Norris, vice president of Cypress’s Data Communications Division. "The Vichara 81000 enables the next generation of packet processing by acting as a central controller in the search subsystem and providing the NPUs and ASICs with the bandwidth to achieve their full potential."
The Need for Speed
Current data-plane packet processors (NPUs or ASICs) perform parsing, routing, policy resolution, modification and scheduling of packets on the linecard. In addition, the control processor concurrently performs control updates in-band through the packet processors on the data path. As wirespeed increases from 2.5 Gbps to 40 Gbps, these processors are unable to perform all the functions without additional assistance. The problem is aggravated by an increased need for policy enforcement to provision higher layer services and deeper network tables to handle the growing number of devices on the Internet. The Vichara 81000 coprocessor helps alleviate this problem.
Designed to supervise the search sub-system on the linecard, the Vichara 81000 connects seamlessly with the packet processor through the LA-1 bus; with NSEs and NoBL SRAMs through their native buses; and with a control processor through the PCI bus interface. After downloading the packet data and search instructions from the packet processor, the coprocessor manages the search system consisting of NSEs and SRAMs. With its unique search management capabilities of conditional branching and recursive search features, the Vichara 81000 is able to coordinate the execution of multiple classes of lookups (for example, access control lists, forwarding and QoS lookups) across multiple contexts from multiple packet processors, returning only the final results to the processors.
Having a search supervisory coprocessor also simplifies hardware and software design for the linecard since the designer can fine-tune the search-system performance through a full suite of Vichara 81000 hardware features and software. In addition to simpler hardware and software design for search systems, the coprocessor’s unique search management system translates to wider and deeper search tables, since multiple NSEs and SRAMs can be cascaded to Vichara.
The Vichara 81000 solves the LA-1 bus bottleneck by offloading search management from the packet processors. Due to its narrow width—18 bits (including two parity bits)—the standard LA-1 bus faces severe congestion resulting from multiple lookups per packet required to process each packet. For a typical Packet over SONET (POS) application, congestion can run as high at 95% at 10 Gbps for lookup functions only. Since the same LA-1 bus is used for other SRAM-related functions, this high bus congestion can ultimately increase system latency significantly. By aggregating search instructions and related data from the processor side of the LA-1 bus and running them on the NSE/SRAM side, Vichara drastically reduces the LA-1 bus congestion (down to 24% from 95% for the POS application referenced above). Reduced bus congestion means lower search latency and use of fewer Packet processor LA-1 ports for search processing.
About Vichara 81000
The Vichara 81000 is a true packet coprocessor, offloading the entire range of search instruction sequences and associated packet data from ASICs and NPUs and managing multiple Layer 3 through Layer 7 searches. Operating at 266 MHz, the Vichara 81000 manages the search operation by working with multiple Cypress Network Search Engines for search indices and NoBLTM (No Bus LatencyTM) SRAMs for the associated data. The Vichara 81000 can interleave and execute multiple contexts in parallel for up to four packet processors supporting up to 64 contexts on each of its four ports. For LA-1 compliant NPUs—including those from Intel, AMCC and IBM—the coprocessor’s search offload translates into significantly higher efficiency for the LA-1 bus.
About Cypress’s Network Search Engines and Coprocessors
Cypress offers the industry’s widest selection of network search solutions, including network search engines and network coprocessors. Cypress’s packet processing solutions are ideal for use in routers, switches and other high-performance networking infrastructure systems.
Cypress’s AyamaTM 20000 family of NSEs consists of multiple densities, ranging from 128K IP (4.5Mb) to an ultra-large 512K IP entry (18 Mb) device. All the members of this family will contain a robust feature set including exceptional performance — as fast as 266 million searches per second (MSPS) — plus MiniKeyTM power management and Soft PriorityTM table management. Through the MiniKey feature, power consumption can be reduced by as much as 70% by only activating the section of the array being utilized. The Soft Priority feature eliminates the latency associated with routing table updates by dynamically prioritizing entries for the longest prefix match (LPM) in Layer 3 forwarding applications. Cypress’s NSEs, coupled with leading NPUs, provide an important combination of characteristics that are necessary for high-end network infrastructure development. That, along with Cypress’s backplane and port solutions, comprises a complete communications linecard portfolio.
Cypress’s broad array of products includes the current 32K-, 64K-, 128K-, 256K- IP entry NSE70000 family. The current devices are configurable from 34- to 288-bit data widths to support Layer 2 to Layer 7 applications. These NSEs can search the network database at up to 100 MSPS enabling wirespeeds processing at speeds greater than 2.5 Gbps. Cypress’s network coprocessor manages the interaction between existing industry standard network processors and Cypress NSEs. The NCP80192 coprocessor accelerates packet processing by offloading tasks from network processors and facilitating database management. The coprocessor’s programmable 32-channel descriptor ring supports multiple contexts, each of which can be programmed independently.
Cycle-accurate software simulation models and associated application programming interfaces (APIs) are scheduled for the first quarter of 2003 along with full software and applications support for alpha customers.
Production samples of CYNCP81000 (Vichara 81000) will be available Q3 2003 in a 484-pin BGA with prices starting at $250 in quantities of 1,000. An evaluation board, device drivers API, full system collateral and Cypress worldwide sales and applications support will be also be available.
Cypress Semiconductor Corporation (NYSE: CY) is Connecting From Last Mile to First MileTM with high-performance solutions for personal, network access, enterprise, metro switch, and core communications-system applications. Cypress ConnectsTM using wireless, wireline, digital, and optical transmission standards, including Bluetooth, USB, Fibre Channel, SONET/SDH, Gigabit Ethernet, and DWDM. Leveraging its process and system-level expertise, Cypress makes industry-leading physical layer devices, framers, and network search engines, along with a broad portfolio of high-bandwidth memories, timing technology solutions, and programmable microcontrollers.
Cypress and the Cypress logo are registered trademarks of Cypress Semiconductor Corporation. "Connectivity From Last Mile to First Mile", "Cypress Connects," NoBL, No Bus Latency, Ayama and Vichara are trademarks of Cypress.
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