10/9/2002 - Altera announced new, smaller form-factor packages for the StratixTM device family, giving system developers the ability to harness the power of the industry's leading high-performance FPGA device without sacrificing board space. With densities up to 18,000 logic elements, the EP1S10 and the EP1S20 Stratix devices will be made available in the space saving 23 x 23 mm FineLine® BGA 484 pin package with immediate Quartus® II development software support.
"The acceptance of Stratix is tremendous, and we are seeing quite a bit of demand for a smaller form-factor package for Stratix devices," said Steve Mensor, senior director of new product marketing for Altera. "As a result of customer input and our ability to quickly respond to customer needs, the new F484-pin package will bring the well known memory, DSP and performance advantages of Stratix to a broader audience."
The EP1S10 and the EP1S20 devices will be available in the thermally-enhanced flip-chip F484 pin package in speed grades -5, -6 and -7. The F484 package also supports vertical migration between the EP1S10 and the EP1S20 devices. The EP1S10 device features 10,570 logic elements (LEs), 920,448 bits of TriMatrixTM memory, and 6 digital signal processing (DSP) blocks while the EP1S20 device offers 18,460 LEs, 1,669,248 bits of TriMatrix memory, and 10 DSP blocks. Industrial temperature grade devices will also be offered in the new F484 package.
Availability and Pricing
Samples of the F484 pin package for both the EP1S10 and EP1S20 devices will be available in December 2002. The EP1S10 F484 pin package has prices starting at $70 for volumes greater than 100,000 units in the mid-2003 timeframe. The EP1S20 F484 pin package has prices starting at $110 for volumes greater than 50,000 units in the mid-2003 timeframe.
The new F484 pin package offering is supported in Quartus II version 2.1 service pack 1 design software available from Altera today. The Quartus II version 2.1 service pack 1 software provides compilation and pin-out support for the F484 pin package to enable customers to start designing with the new package today. Using the free Quartus II Web Edition software, developers can target designs to the Stratix EP1S10 device. The Quartus II Web Edition version 2.1 software is a free, downloadable design, place-and-route, and verification tool that comprises the basic features and functionality of the recently introduced Quartus II version 2.1 software. It is available from the Altera web site.
Stratix devices are based on a 1.5-V, 0.13-micron, all-layer copper SRAM process, with densities ranging from 10,570 to 114,140 logic elements (LEs) and up to 10 Mbits of RAM. Stratix devices offer up to 28 DSP blocks with up to 224 embedded multipliers, optimized for DSP applications that require high data processing. Stratix devices support various differential I/O electrical standards such as the LVDS, LVPECL, PCML and HyperTransportTM standards, as well as high-speed interfaces, including the UTOPIA IV, SPI-4 Phase 2, SFI-4, 10G Ethernet XSBI, RapidIOTM, HyperTransport and other interfaces. Stratix devices also offer a complete clock management solution with its hierarchical clock structure and up to 12 phase-locked loops (PLLs).
Altera Corporation (NASDAQ: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide.
Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations and all other words that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries.
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