10/2/2002 - Xilinx announced a new reference design program designed specifically for the company's leading line of CoolRunner® CPLDs. The free drop-in designs are available for a wide range of applications, from portable consumer applications, to wireless transceivers and high performance memory interfaces. The downloadable reference designs provide everything a designer needs to reduce product development time, including complete HDL source code and detailed application notes. The designs support the entire line of CoolRunner CPLDs, including the latest CoolRunner-II family of devices introduced earlier this year. Combining high performance, ultra low-power, and the highest I/O count per macrocell of any competing device, CoolRunner-II RealDigital CPLDs are cost optimized to address the increasing demands of today's system designer.
"The CoolRunner-II Reference Designs address the increasing demands of today's networking, telecommunications and portable system designers," said Evert Wolsheimer, vice president and general manager of the CPLD division at Xilinx. "Designers can now focus their efforts where they count most - on getting their product to market before the competition, while managing overall development costs."
About CoolRunner-II RealDigital CPLDs
CoolRunner-II RealDigital CPLDs provide the time-to-market advantages of a programmable device without the typical price premium normally associated with low power devices. Available in densities ranging from 32 to 512 macrocells, the CoolRunner-II family achieves performance of over 300 MHz and pin-to-pin delays as fast as 3.5ns while providing a standby current of less than 100 microamp (<100uA) - an industry first. The CoolRunner-II Fast Zero Power™ (FZP) design technology creates a new class of CPLD that utilizes a 0.18 micron process and 1.8V core voltage to provide both high performance and ultra low-power consumption in a single device.
Xilinx, Inc. (NASDAQ: XLNX) is the worldwide leader of programmable logic and programmable system solutions.
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