10/1/2002 - Synopsys, the technology leader for complex integrated circuit (IC) design, announced its entry into the logic BIST market with DFT CompilerTM SoCBIST offering deterministic logic BIST capabilities. Compared to full scan, SoCBIST provides designers significant savings in test cost by reducing test time and data volume, while deterministically retaining scan's very high fault coverage. It is transparently integrated within Synopsys physical synthesis flows, thereby ensuring designers that design-for-test (DFT) closure and timing closure are always achieved.
"NVIDIA has long recognized the limitations of traditional test methodologies as applied to high volume products with the performance levels and device sophistication of our graphic and platform processors," said Chris Malachowsky, co-founder and vice president of hardware engineering at NVIDIA Corporation. "Our adoption of Synopsys' SoCBIST overcomes these limitations allowing us to improve test coverage while simultaneously reducing the cost of test. Our first application of this technology was on a 20 million gate device. The results have exceeded our expectations, showing off both the capability and maturity of this innovative new DFT platform."
"We have seen excellent test data volume and tester time reduction with Synopsys' SoCBIST - from RTL synthesis to gate-level diagnostics - and are very satisfied," said Seiichi Nishio, senior manager, System LSI Design Division, Semiconductor Company, Toshiba Corporation."SoCBIST is a straightforward extension of the Synopsys DFT CompilerTM and TetraMAX® ATPG design flows we use. We will use SoCBIST in upcoming ASSP products and intend to deploy SoCBIST within Toshiba design teams."
To meet strict product quality mandates without increasing the cost of design and test, designers need a DFT solution that provides predictable high fault coverage, requires minimal automatic test equipment (ATE) usage, and does not impact the overall design flow. Synopsys' SoCBIST meets these requirements, reducing tester time by more than 10 times and reducing data volume by 100 to 400 times compared to traditional scan. Additionally, SoCBIST needs 20 or fewer ATE pins and requires less than 1 percent of the vector memory required by a full scan approach.
SoCBIST is transparently integrated within the Synopsys Design CompilerTM and Physical CompilerTM flows. It is an extension of Synopsys' unique 1-pass test synthesis flow, which enables designers to use SoCBIST directly within the physical synthesis environment. This eliminates costly iterations between design synthesis and test implementation and enables IC designers to achieve timing and DFT closure simultaneously. In addition, SoCBIST provides comprehensive and easy-to-use design rule checking and validation features, as well as powerful BIST integration, verification, diagnostic and debug tools.
"Our customers are faced with the conflicting demands of producing the highest quality products while reducing their overall test cost, and they are looking to us for a solution," said Antun Domic, vice president and general manager of Synopsys' Nanometer Analysis and Test business unit. "Since SoCBIST is integrated within the industry-standard Synopsys synthesis flow, we enable our customers to preserve their existing investments in design and test automation tools and still achieve higher quality results at a lower cost."
Pricing and Availability
SoCBIST is an add-on to DFT Compiler and will be available in a controlled availability basis with the September 2002 production release. Pricing for the DFT Compiler SoCBIST add-on begins at $175,000 US list price for a one-year technology subscription license (TSL).
Synopsys Test Automation Solution
Synopsys provides a complete test automation solution to meet the most demanding DFT and manufacturing test requirements. The company's award-winning product offering includes DFT Compiler and TetraMAX ATPG tools. DFT Compiler incorporates the latest generation of Synopsys' patented 1-Pass test synthesis technology and enables design teams to efficiently meet their DFT closure goals. TetraMAX complements scan-based test methodologies by providing a comprehensive delay test capability as well as high ATPG performance, capacity and ease of use.
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, Calif., creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers.
Synopsys, the Synopsys logo and TetraMAX are registered trademarks and DFT Compiler, Design Compiler, and Physical Compiler are trademarks of Synopsys, Inc.
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