10/1/2002 - Cypress Semiconductor introduced its next-generation high-performance QuadPort® Datapath Switching Element (DSE), which supports bandwidths up to 27 Gigabits per second (Gbps) and provides densities up to 5 Mbits. Cypress’s QuadPort DSE is a four-port switching element that allows simultaneous access to an integrated memory array from each of its completely independent ports which can operate in different frequency domains. The family can help eliminate contention and arbitration issues on a shared bus when multiple processors or functional blocks need access to the same data, thereby significantly improving overall system performance.
Cypress pioneered the concept of QuadPort DSEs with the introduction of its one Mbit family (10 Gbps bandwidth) in 2001, including functions such as 2 x 2 switching, datapath aggregation, redundant data generation and packet header manipulation. This next-generation QuadPort DSE family adds higher bandwidth (4 ports x 167 MHz x 40 bits) and higher storage capacity (up to 5Mbits). At these unprecedented levels of performance and storage, Cypress doubles the bandwidth and over quadruples the density of any competitive offerings.
"These high-performance devices put Cypress a generation ahead of the competition and allow our customers to create innovative system architectures, thereby achieving higher performance and efficiency," said Geoff Charubin, marketing director for Cypress’s Data Communications Division. "By providing up to 5 Mbits of integrated memory at 27 Gbps operation, the QuadPort DSE enables our customers to reduce the need for multiple devices, thereby significantly improving their cost-per-megabit of capacity and cost-per-gigabit of bandwidth."
QuadPort DSE Innovates System Architecture
The QuadPort DSE shows its strength as a communications datapath enabler because its combination of logic and memory creates a non-blocking switch architecture. Maximum system benefit is gained by planning for usage during the architectural stage of design. For example, the devices may be used as:
a 2 x 2 switch fabric among four devices such as field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), application specific integrated circuits (ASICs), PHYs or a series of digital signal processors (DSPs)
a data-path aggregator that allows multiplexing multiple low-bandwidth data streams into a single high-bandwidth data stream
a redundant data-path generator that allows users to input a single stream of data into one port and then output identical data streams at variable data rates on each of the other ports for fault tolerance and parallel processing
a packet-header manipulation engine that uses two ports to read and write an entire packet and one or two ports to monitor and/or change the header, which provides an alternative for high-cost data-path FPGAs by lowering its logic-gate count, I/O number, and internal memory requirements
When used in conjunction with the Cypress OC-48 port SERDES, Delta39KTM CPLDs and HOTLink® family of backplane physical-layer devices, the QuadPort DSE family provides a complete system solution for customers building communications linecards. Communications systems customers who are already familiar with Cypress’s Quad Data RateTM RAM, BEASTTM FIFO, synchronous SRAM, CPLD, and clock solutions will also benefit from the QuadPort DSE Family.
QuadPort DSE Features
This QuadPort DSE family of devices offers configurable I/Os supporting LVTTL and SSTL2 standards, enabling seamless interface with PLDs, FPGAs, ASICs, next-generation DSPs, control processors and other memory devices on the board. These devices also come with advanced features such as impedance matching on data outputs to reduce transmission line effects; burst counters for enabling block transfer of data; and memory block retransmit for rereading a block of data in case of transmission failure.
All QuadPort DSEs offer four completely independent ports that can simultaneously access the data storage array and operate in different frequency domains. Each port can read or write data up to 167 MHz, giving the device up to 27 Gbps of data throughput or bandwidth. Offered in a 676-ball PBGA package measuring 27 mm x 27 mm with a 1.0 mm pitch, these devices are compliant with IEEE 1149.1 JTAG boundary scan for a high degree of manufacturability.
Cypress Semiconductor Corporation (NYSE: CY) is Connecting From Last Mile to First MileTM with high-performance solutions for personal, network access, enterprise, metro switch and core communications-system applications. Cypress ConnectsTM using wireless, wireline, digital and optical transmission standards, including Bluetooth, USB, Fibre Channel, SONET/SDH, Gigabit Ethernet and DWDM. Leveraging its process and system-level expertise, Cypress makes industry-leading physical layer devices, framers and network search engines, along with a broad portfolio of high-bandwidth memories, timing technology solutions and programmable microcontrollers.
Cypress, the Cypress logo, HOTLink and QuadPort are registered trademarks, and "Connectivity From Last Mile to First Mile," "Cypress Connects," Delta39K and BEAST are trademarks, of Cypress Semiconductor Corporation. QDR and Quad Data Rate are trademarks of the QDR Consortium.
Previous Page | News by Category | News Search
If you found this page useful, bookmark and share it on: