1/15/2002 - Corelis Inc., introduced today a new boundary-scan Design-for-Test (DFT) tool, ScanPlusDFT Analyzer, which generates test coverage summary and detailed reports for all the nets and pins on the board under test. Boundary-Scan, also known as JTAG, is an embedded IC technology for testing digital circuit boards and components that has been standardized as IEEE Std 1149.1. Until now, finding precisely the test coverage of boards that include boundary-scan components was a daunting task. There was no automatic way to quantify increase in test coverage when more test steps, such as memory tests, were added to the test plan. Now the use of ScanPlusDFTä Analyzer reduces the test coverage analysis time to seconds. It also precisely classifies nets and pins by level and type of testability coverage.
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