Error Correction Control for Embedded Memory to be Featured in Design Con 2002 Paper Delivered by ATMOS Corporation

1/21/2002 - System-on-a-chip (SoC) designers developing solutions for applications that rely on secure and accurate data transfer — such as networking, encryption and compression/decompression — are concerned about how soft errors affect their SoCs and intellectual property cores. ATMOS Corporation will address this important topic in a DesignCon 2002 presentation on the use of error correcting code (ECC) to reduce soft error rate (SER) in embedded memory. Entitled, “An Embedded DRAM Memory Architecture for High-speed Network Processors,” the paper will be presented on Tuesday January 29, 3:00-3:50PM.

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