IC Tools News
- Cadence Synthesis Speeds Time to Market for Hitachi Communication
- VIS Improves Verification Time by 10x with Cadence Virtuoso Platform
- Sun Verifies UltraSPARC T1 Processor with Cadence Incisive Xtreme Server
- STARC Certifies Sequence's PowerTheater and CoolTime for STARCAD-21
- Cadence Design Speeds Adoption of Incisive Plan-to-Closure Methodology
- Sequence Targets Sub-90nm with Next Generation PowerTheater Design Suite
- Real Intent Rolls Out Next Generation Clock Domain Verification Tool
- SDC Validates Enhanced Power Management Methodology with ARM 1136JF-S
- Cadence, IBM, Chartered Create 90-nm Low-Power, Yield-Aware Reference Flow
- Sequence Unveils Latest Columbus-AMS RLC Parasitic Extraction Tool
- STMicroelectronics Develops HDTV Decoder with Cadence Encounter Platform
- Cadence Debuts Virtuoso Resolution Enhancement Technology (RET) Suite
- Cadence X Architecture Wins IEC DesignVision Award for ASIC, IC Design Tool
- Genesis Microchip Selects Sequence Voltage Drop and Power-Grid Integrity
- Cadence Virtuoso UltraSim Speeds Design, Verification for Sirific Wireless
- Cadence Develops Chip Optimizer with Manufacturing-Aware Technology
- D'GIPRO Distributes Pulsic's Shape-Based IC Physical Design Platform
- Fujitsu Adopts Cadence Encounter Platform for 65nm Reference Design
- MIET Selects Cadence Tools to Develop Russian Electronics Industry
- Cadence Offers EDA Tools on Sun Solaris 10 for SPARC, x64 Platforms
- Cadence Upgrades Incisive Enterprise Specman Elite for SoC Verification
- Cadence SoC Encounter GXL Addresses Challenges at 65nm and Beyond
- Cadence Design Systems Rolls Out Encounter RTL Compiler GXL
- Cadence Encounter Conformal Low Power GXL Targets 65nm and Beyond
- Cadence Encounter Helps P.A. Semi Develops 65nm, Multicore Processor
- Cadence Incisive Enterprise Links Multiple Specialists and Languages
- Hitachi Reduces Overall Verification Risks with Cadence Palladium II
- Freescale and Cadence Focus on Innovating Semiconductor Product Design
- Kawasaki Micro Completes 30+ Tapeouts with Cadence Encounter Synthesis
- Cadence Introduces 3 Tiers of Verification Products and Methodologies
- Virtio Empowers Embedded Designers with Cycle-Approximate Simulation
- Cadence's Incisive Design Team Enables SystemVerilog from Plan to Closure
- Cadence Introduces Design Flow for ARM's Cortex-A8 Processor
- Toshiba Tapes Out UniversalArray (UA) Chip with Cadence Encounter
- Cadence Encounter Digital IC Design Platform Helps S3 Complete 65nm Chip
- Calypto, Forte Integrate Formal Verification and Behavioral Synthesis
- YOGITECH Creates Automated Mixed-Signal Verification Component Kit
- SofTec Announces New Starter Kit for Freescale MC68HC908EY Devices
- EVE Debuts ZeBu-UF Next-Generation Hardware-Assisted Verification Platform
- Comit Systems Commits to Encounter RTL Compiler Global Synthesis
- Experts Conclude 193nm Immersion Litho on Track for 45nm Half Pitch
- New Cadence Physical Verification System Dramatically Reduces Run Time
- Cadence Creates AMS Kit for Wired, Wireless, Consumer Electronics
- Cadence Addresses Growth in Chip Complexity with Segmentation Strategy
- Accellera Approves Open Verification Library (OVL) 1.0
- Cadence Addresses Complex Packaging Needs with New Allegro Technology
- ArchPro Creates World's First Multi-Voltage RTL Simulation Product
- Cadence Synthesis Technology Improves Quality of Silicon for Global Unichip
- Cadence Encounter RTL Compiler Shrinks DVD Chip Size for SunPlus
- Fujitsu to Ship New Structured ASIC Built Using Cadence Encounter
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