IC Tools News
- China Suzhou CAS IC Design Center Selects Cadence for IC Design
- Cadence Develops Most Accurate Cell-Based Extractor with Fire & Ice
- Aspex Delivers Software Programmable Processors with Cadence Tools
- Synopsys Sets Standard for Renesas with Galaxy Design Platform
- Global Unichip Selects Cadence Encounter for IC Platform
- Magma's Blast Fusion Integrate Part of Wipro IC Design Flow
- Mentor Unveils Capital Logic Data-Centric Wiring System Design Tool
- Faraday Adopts Mentor Graphics Calibre xRC for Parasitic Extraction
- Agilent Debuts Cost-effective 93000 SOC DFT Series
- ASE Group Expands ICs Testing Capacity with Agilent 93000 SOC Series
- Matsushita Reduces Verification Runtime to Minutes with Cadence Tools
- Hua Hong NEC IC Foundry Standardizes on Mentor Graphics Calibre
- HCL Technologies Joins MagmaTies Design Services Partnership Program
- Tensilica Goes to PowerTheater with Sequence for RTL Power Analysis
- Metalink Encounters Nanometer Technology with Cadence Platform
- Virage Logic Supports Chartered Semiconductor's 0.13-Micron Process
- Magma Welcomes Silicon Metrics to MagmaTies Partner Program
- Cadence Optimizes, Qualifies IBM Nanometer Technology with Reference Flow
- Cadence Provides EDA Solutions to Shenzhen IC Base
- Verisity, 0-In to Develop Testbench, Assertion Coverage Metrics
- TSMC Encounters Cadence's Digital IC Platform for Nanometer Designs
- Synopsys Addresses Crosstalk Delay with Galaxy Enhancements
- Synopsys' Star-RCXT Delivers 90-nm Parasitic Extraction for Toshiba
- Mentor Directs Infineon's Nanometer Design with TestKompress, Calibre
- Magma Integrates ALF Standard into Blast Fusion with ASC ALF Parser
- Cadence Design Systems Showcases Products at DAC
- Cadence Leads with Vision at DAC
- Magma Brings Synthesis, Power and Noise to DAC
- ARM, NVIDIA Select Cadence Incisive Verification for Nanometer ICs
- Goyatek Succeeds with .13-Micron ISSI Design with Magma Blast
- Cadence Makes First Encounter with Infineon 130nm, 90nm Prototyping
- Sequence Adds New 90nm Features in Next-generation PhysicalStudio
- Magma's Physical Design System Enables DSM SoC Solutions for CPU Tech
- OpenAccess Powers Cadence Virtuoso Chip Editor Chip Finishing by 10x
- Sequence Speeds Development of NVIDIA Graphics Processors
- Synopsys DFT Compiler SoCBIST Powers ATI Upcoming Visual Processor
- Cadence Speeds Network Processing Chipset Development for Teradiant
- Mentor Graphics Multi-flexes Nanometer Design with Calibre MTflex
- WIS Tech Develops 5M Gate, 0.18 Video Compression Chip with Magma Tools
- Magma Blasts Off with Rail Design Solution for Nanometer Design
- Mentor Graphics Emulates Silicon Graphics' Next-generation Systems
- Sequence Physical Studio Leads to NEC First-Silicon Success
- Toshiba Produces Fastest Synthesizable 64-Bit MIPS Core with Cadence Encounter
- Magma Announces Blast Create Front-End IC Design Flow
- Astek Develops Partitioning Tool for Atmel-based ASIC Design Validation
- Synopsys' PrimeTime Sets New Timing Sign-Off Standard In the Galaxy Design Platform
- Cadence DFT TestBench Supports 64-bit AMD Opteron Processor on Linux
- Mentor Graphics Introduces IP-Xpress Target Verification Platform
- Mentor Rolls Out Calibre Products with Support for Toshiba Mask Writing
- Magma's Design Flow is Ready for IBM
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