IC Tools News
- Agere Systems Honors Cadence with Strategic Supplier Award
- Motorola Tapes Out Reconfigurable Compute Fabric Device with Cadence
- Carbon Design Systems Enables Pre-silicon Validation with Tools Suite
- Fujitsu Licenses Three Verification Technology Patents to Cadence
- Synopsys Galaxy Supports AMD64 Processors on Red Hat Enterprise Linux
- Sequence Columbus-AMS Sets 90nm Standard for Renesas Technology
- 0-In Design Automation's Assertion Synthesis Tool Speaks Many Languages
- Cadence Encounters 100th Tapeout with NanoRoute Router
- Synplicity Accelerates Verification with New RTL Prototyping Software
- Magma Certifies GarField for MagmaTies Design Center Program
- Verisity, 0-In, Novas Address Nanometer SOC Verification Challenges
- Virtual Silicon Offers Signal Integrity Views for 130nm Standard Cells
- NEC Electronics, Synplicity to Develop Custom Physical Synthesis Software
- Renesas Signs Off with Cadence SignalStorm NDC for 90nm Flow
- Teradiant Tapes Out Two Multi-million Gates with Magma Blast Fusion
- Synopsys, Toshiba Create Media Embedded Processor Reference Design Flow
- Magma Gains 3D Field Solver by Acquiring Random Logic
- Magma's RTL-To-GDSII System Enables Broadcom's 15-Million-Gate Design
- Infrant, NEC Tapes Out 3-Million-Gate ASIC with Magma RTL-to-GDSII
- Chrontel Designs Digital Visual Interface Chip with Magma's Design Flow
- Magma RTL Synthesis Makes ASIC Handoff to NEC Electronics
- Veritools Undertow Tool Meets Magma Blast Create Synthesis Solution
- Blast Create Gives QuantumThink RTL-To-GDSII Design Expertise
- Spike Technologies Supports Magma's Blast Create
- STMicroelectronics Designs 130nm XM Radio with Cadence Encounter
- Cadence Creates Complete IC Package and PCB Design Flow for Linux
- Magma on Fastrack for Turnkey RTL-to-GDS Flow Design
- More Than 300 Licenses Adopts Magma Synthesis Solution
- Cadence Unveils Integrated IC Packaging Design and Signal Integrity Tool
- Magma Receives Qualification from NEC for Mainstream Production Use
- Cadence Accelerates High-End Digital IC Design with Encounter 3.2
- Mentor's Calibre xRC is Parasitic Extraction Tool of Choice for Zoran
- Cadence Encounter Improves Timing and Placement, Speeds Digital IC Design
- Xilinx Delivers Process Technology Opportunities to IEEE CICC
- Mentor Improves 90nm Support by Joining Chartered NanoAccess Alliance
- Fire & Ice Leads Cadence, Chartered to 90-nm IC Design Solutions
- Synopsys DFT Compiler SoCBIST Helps Toshiba Tapes Out 6 Million Gates
- Encounter Results in ARM-Cadence Reference Methodology
- Magma Targets AMD Opteron, AMD64 Architecture with RTL-To-GDSII Support
- AMCC Reduces Time to Take Design Concept to Silicon with Magma Tools
- Agere Tapes Out Network Processor with Synopsys' Galaxy Platform
- Toshiba Tapes Out 2.5-Million-Gate SoC in 4 Weeks with Magma Software
- Synopsys’ Star-RCXT Powers 90 Nanometer Cell-Based LSI Design for NEC
- Fusion Conference Melds Magma Users with Design Expertise
- Cadence, CoWare Standardize System-to-Silicon Design Solution
- Cypress Spins Off Portion of NVE's Spintronics Technology
- Magma Presents IC Design Challenges and Opportunities in Shanghai
- Mentor Graphics Enhances Wire Harness Engineering Software
- Agilent Helps Establishes China's First IC Testing Development Center
- NVIDIA Verifies PCI Express Designs with Denali Tools
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