IC Tools News
- Synopsys Supports MIPS 24K with Galaxy Design Platform Reference Flow
- Artisan Supports Magma Blast for 0.13-micron and Smaller Process
- Rising Tapes Out 10 Gbps Optical Transmission IC with Cadence Virtuoso
- Engim Develop 2-Million-Gate, Multi-Channel 802.11 Chip with Magma
- Future Horizons Unveils Programme for International Electronics Forum
- Motorola Takes Synopsys 90nm Phase-Shifting Technology Global
- Manheim Award Flows to Fujitsu Chief Architect for Workflow Work
- Motorola Develops 90nm Wireless Baseband Chip with Cadence Encounter
- Procket Networks Selects Cadence Encounter RTL Compiler for Synthesis
- Cadence Encounter RTL Compiler Synthesis Rolls into Agere's ASIC Centers
- Philips and IMEC Continue Focus on Developing Semiconductor Processes
- Synopsys' Star-RCXT Receives TSMC Certification for 90-nm Designs
- Honeywell, Synopsys to Develop Design Flow for Radiation-Hardened IC
- Cadence Optimizes Virtuoso Platform New Chip Integration Flow
- Magma's Blast Fusion Passes 500 Tape-out Milestone
- Sycon Tapes Out .18-micron, 180-MHz Design with Magma Blast Tools
- Magma Combines DFM-aware IC Implementation Flow with Mojave Technology
- Synchronicity Accelerates Chip Design with Synopsys' Milkyway Platform
- Magma, ARM Debut Reference Methodology for RTL-to-GDSII Implementation
- Magma's SiliconSmart Characterization and Modeling Sets Standard for NVIDIA
- Synopsys Improves Proteus Optical Proximity Correction Software
- Nassda Joins MagmaTies to Collaborate on Nanometer Design Solutions
- Cadence, ARM Deliver New Generation Digital Reference Methodology
- Static Timing Analysis Performance Standard Improves with PrimeTime
- Magma Users Group Changes to MUSIC and Expands
- Gennum Designs Ultra Low Power Microprocessor with Target's Chess/Checkers
- EDN Nominates Magma's Blast Rail for Innovation of the Year
- Toshiba to Enter 65nm Production with Synopsys PSM Technology
- Magma Highlights Synthesis, Power & Noise Management, Modeling at DATE
- Toshiba Extracts with Sequence Columbus-AMS RCL Extraction Tool
- Renesas, Mitsubishi Blast their Way to 10-Million-Gate Design
- ATI Gains Access to Synopsys Design and Verification Technology
- Motorola Signs Off with Mentor Graphics TestKompress and Calibre
- Synopsys Gains AMS Technologies by Acquiring Analog Design Automation
- 0-In Targets Multi-million Gate Designs with Archer Verification System
- Major Intellectual Property Vendors Roll Out Magma-Ready IP
- Toshiba Implements 3-million-gate SoC with Magma's Blast Create
- Magma's RTL-to-GDSII IC Design Flow Sets Standard for Legerity
- Cadence and 0-In to Deliver Superior Assertion-Based Verification
- IBM ASIC Group Validates Magma's Blast Create RTL Synthesis Solution
- Cypress Flows at 130 and 90 Nanometer with Cadence Fire & Ice
- Cadence Adds Process Migration with Q Design Automation Acquisition
- CVR Engineering Students Benefit from Cadence VLSI Design Tools
- Magma Trains Designers with IC Excellence Initiative in India
- Sun Continues Commitment to 0-In's Assertion-Based Verification Suite
- ClearSpeed Delivers Highest Performance Floating-Point Chip with Magma
- ClearSpeed Clearly Achieves First-pass Silicon Success with Magma Tools
- Mentor Accelerates Engineering Change Order Processes with ECO Cockpit
- Faraday Develops MPCA Design Flow with Cadence Encounter Platform
- Cadence Encounter to Support NEC's ISSP Structured ASIC Platform
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