IC Tools News
- Synopsys Supports IBM-Chartered 90nm Process with Galaxy and Discovery
- IBM and Chartered Approve Calibre for 90nm Design Enablement Platform
- Cadence Supports IBM-Chartered Process Platform with 90nm Reference Flow
- Precision Enables Altera Customers to Reach Timing Closure Quicker
- Sequence Targets 90nm SoC Designs with Columbus-NTX Extraction Tool
- Nohau Elektronik Distributes PolySpace's Static Verification Tools
- PLDApplications Develops PCI Express Core Products with Denali's PureSpec
- T3G Develops TD-SCDMA Mobile Phone Chipset with Cadence Incisive
- Magma, Faraday Unveil RTL-to-GDSII Flow for Structured ASIC Platforms
- Aspex Implements 130nm Linedancer Processor with Cadence Encounter
- 0-In Automates Verification of Metastability Effects with Archer
- Cadence Rolls Out NanoRoute Super-threaded Route Acceleration
- Cadence True-Time Delay Test Delivers Timing to Manufacturing Floor
- 0-In Archer 2.2 Improves Efficiency of Coverage-Driven Verification
- Magma Improves Blast Fusion APX Physical Design System
- Cadence Heads to DAC with Digital Nanometer SoC Design Flows
- Magma Unveils Blast Create 4.2 RTL-to-placed Gates Solution
- Synopsys Speeds Out Galaxy 2004 Design Platform with 2x Enhancements
- Magma Targets FPGA and Low-cost Structured ASIC Designs
- Magma Rolls Out Blast Plan Pro 4.2 with Black-box Methodology
- Magma Introduces Enhancements to Embedded Analysis Engines
- IIT Kharagpur Tapes Out Chipsets with Cadence Virtuoso Platform
- Sequence and Golden Gate Offer Power Integrity Flow for Nanometer SoCs
- Magma to Offer Hands-on Tutorial and Product Demonstrations at DAC
- Calibre Design-to-Silicon Platform Integrates with OpenAccess Database
- Hierarchical Netlisting Takes Calibre xRC Parasitic Extraction to Simtek
- Synopsys Enhances SiVL Silicon-Versus-Layout Verification Tool
- Industry Leaders Reduce Verification Bottlenecks with Cadence Incisive
- Magma QuickRules Integrates QuickCap Technology into Blast Fusion APX
- UMC, Synopsys Debut Reference Flow for Advanced Deep Submicron Processes
- Magma Targets Power Optimization and Management with Blast Power
- Magma to Create Low-Power RTL-to-GDSII Reference Flow for Blast Power
- Mentor and X-FAB Unveil Design Kits for Mixed-Signal IC Design Flow
- Synopsys' Galaxy Takes Toshiba to Multiple 90-Nanometer SoC Designs
- NEC to Deploy Magma's Complete Line of IC Implementation Solutions
- Synopsys' Galaxy Leads NVIDIA Leads to GeForce Graphics Processor
- Magma Unveils Quartz Formal Verification Tool with IBM Technology
- QualCore Logic Verifies PCI Express Core with Denali's PureSpec
- UMC, Cadence Target Mixed-Signal Designs with Analog Reference Flow
- Sequence Receives Patents for Analysis and Optimization of Chip Design
- Synplicity Enables Debug-Centric Verification with Identify RTL
- Synplicity Enhances Certify Prototyping Software for Large ASICs
- Mentor Updates VStationTBX with Full Language Support for System C
- Synopsys and TSMC Collaborate to Optimize RTL-to-Wafer Design Process
- Cadence Receives TSMC's Qualification for Encounter RTL Compiler
- Cadence Encounter Leads to 8-Million-gate Networking Switch for Toshiba
- Magma Blast Fusion Receives TSMC Validation for 0.13-Micron Designs
- Synopsys Sets New Benchmark for Deep Submicron Designs with Galaxy Test
- Cadence Gains Rapid Analog Design Technology by Acquiring Neolinear
- Denali MemCon Series Kicks-Off in Taiwan
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