IC Tools News
- Cadence and UMC Debut Digital Reference Flow for 130nm and Below
- Magma Users share Nanometer Design Solutions at Conference
- IPCore Selects Synopsys Platforms and IP for Primary Design Flow
- Cadence Introduces New CPU/DSP Core-Based Methodology for SOC Chips
- Cadence Encounter Platform Accelerates Time to Market for Stretch
- UMC Selects Mentor Graphics FastScan ATPG Tool for 130nm and 90nm Flow
- FishTail Design Automation Joins 0-In Check-In Partner Program
- Mentor's Tool Improves Designs with Actel's ProASIC Plus FPGAs
- ATI Verifies Complex Multimedia SoCs with Cadence Incisive Palladium
- NVIDIA Reduces Verification Time in Half with Cadence Incisive Palladium
- Airgo Networks Automates Power Analysis with Sequence's PowerTheater
- Mentor Rolls Out Capital Harness Systems 2004.1 for Electrical Design
- Carbon Design Systems Checks into 0-In's Check-In Partner Program
- SMIC Deploys Synopsys' Proteus OPC Software for 130 Nanometer Node
- Synplicity Gains Patent for Signal Integrity Technology
- Magma Turns Users Summit on Integrated Circuits into MUSIC
- Magma Integrates SiliconSmart Technology with MSIM Circuit Simulator
- ATI Develops Radeon X800 High-Speed Graphics Chips with Cadence Encounter
- Renesas Standardizes on Synopsys Star-RCXT for 90 Nanometer Designs
- Cadence Debuts Advanced Verification Environment for Incisive Palladium
- Atmel Verifies Designs with Cadence Virtuoso UltraSim FastSpice Simulator
- Calibre and ModelSim Support 64-Bit Linux - AMD64 Processor Platforms
- Cadence Enhances Virtuoso Platform to Speed Custom IC Design
- Mentor Debuts Technology Design Kit for SMIC 0.18 Mixed-Signal Process
- Tensilica Automates Optimized RTL Block Design from Standard C Code
- Synopsys Encourages Technology Growth in Korea with Galaxy and Discovery
- UMC Validates Calibre xRC Parasitic Extraction Solution for 90nm Process
- Synplicity Rolls Out Synplify ASIC Synthesis Tool for NEC Gate Arrays
- Cadence Debuts Allegro Design Workbench with MatrixOne Technology
- Magma, PDF Create IC Implementation Flow with Embedded DFM and DFY
- Mentor Offers Free GDS-to-OASIS Translator for Download
- 0-In's Archer Verification System Supports SystemVerilog and VHDL
- Mentor Graphics Acquires 0-In Design Automation
- Cadence Introduces First Encounter Global Physical Synthesis
- Cadence and ASML to Develop Advanced DFM Solutions
- Cadence and TSMC Target Low Power Design with Reference Flow 5.0
- Synopsys Galaxy Power Offers 2X Power Reduction for 90nm Designs
- TSMC Reference Flow 5.0 Includes Synopsys Galaxy's Features
- Sequence Design Dramatically Reduces Leakage Power with PhysicalStudio
- Incentia Rolls Out 2004.05 Release of Synthesis and Timing Software
- Sequence Debuts PowerTheater-nm Nanometer RTL-TO-GATE Power Analysis Tool
- Philips Extends and Expands Deployment on Synopsys Galaxy Design Platform
- Magma Validates Parasitic Extraction on UMC's 0.13-micron Processes
- Toshiba Adopts Magma's Blast Fusion APX for 90nm, SoC Product Design
- Agilent Debuts Advanced Design System 2004A Software for Circuit Design
- Cadence Encounter Supports Virage Logic Structured-ASIC Design Libraries
- Renesas Commits to Synopsys' Jupiter XT 90nm Design Planning Flow
- National Semiconductor Standardizes on Synopsys VCS, Leda, Formality
- Synopsys Builds in Testbench with Latest VCS RTL Verification Solution
- Magma Targets IBM-Chartered Process Platform with 90nm Design Kit
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