IC Tools News
- NEC Encounters 90nm Vector Supercomputer Chipset with Cadence IC Flow
- Cadence Encounter Platform Leads Azul to High-Density, High-Speed Chip
- Sasken Accelerates Convergence with Synopsys' Galaxy Design Platform
- NEC Succeeds with Magma's Third-Generation Routing Technology
- Synopsys Supports Intel Xeon Processor with Extended Memory 64
- Mentor Introduces Two New iSolve Verification Speed Adapters
- Cadence Introduces Encounter Conformal 5.0 Formal Verification Tool
- Magma Rolls Out Design Enablement Kit for IBM-Chartered 90nm Process
- Cadence Fire and Ice QX Qualifies for Chartered's Nanometer Processes
- Cadence Sponsors Industry Forums to Address Challenges of Design Chain
- Synplicity Joins LSI Logic's RapidChip Partner Program
- Agilent Announces Free MP3 Player-Voice Recorder EDA Promotion
- Atmel Expands and Extends OEM Partnership with Mentor Graphics
- Latest Libero Design Environment Speeds Actel's Axcelerator FPGAs
- Toshiba Tapes Out 24-Million-Gate Chip with Cadence SoC Encounter
- NVIDIA Maximizes Verification Productivity with Synopsys' Magellan
- ATI Adopts Mentor Graphics VStationTBX for Verification Acceleration
- Cadence Introduces Incisive Palladium II Acceleration-Emulation System
- Magma, Mentor Graphics Integrate TestKompress into RTL-to-GDSII Flow
- Logicvision, Magma Ensure Interoperability Between icBIST, Blast Create
- Magma Files Counterclaims Against Synopsys in U.S. District Court
- HHNEC Reduces Mask Synthesis Turn-Around-Time with Synopsys' Proteus OPC
- Magma Showcases Physically Aware DFT Capabilities Within Blast Create
- Mentor Creates DFM Technology with Calibre Design-to-Silicon Platform
- Magma, Teseda Team for Seamless IC Implementation, Diagnostic, Test Flow
- Cadence Encounter Diagnostics Delivers Higher Yield in Less Time
- Magma Partners with Cadence for Leading-Edge Timing Model Standard
- TransEDA Maintains Growth After Merging Verification Technologies
- Cadence Unveils Comprehensive Assertion-based Verification Solution
- Q-DOT Selects Sequence's Columbus-AMS RLC Parasitic Extraction Tool
- BAE Creates Radiation-Hardened Space-Qualified ASICs with Synopsys' Galaxy
- Synopsys' Circuit Explorer Enables Microchip to Save Analog Design Time
- Artisan and Cadence Provide Library Views for Low Power Devices
- Lattice Adds Mentor's Precision RTL Synthesis to Design Tools Portfolio
- HPL's Cell Designer Addresses Design-for-Manufacturing Issues
- Renesas Reduces Mask-Marking Cycle Times, Costs with Cadence MaskCompose
- Magma Reveals Best Paper Winners for Users Summit on ICs
- ChipIdea Joins MagmaTies Program to Ensure Cores are Magma-Ready
- Atheros Selects Synopsys' NanoSim for Advanced Wireless Chip Verification
- Magma Contends Synopsys Patent Suit are Without Merit
- MIPS Technologies, Magma Debut Reference Methodology for 24K Cores
- Mentor Unveils New Resistance and Capacitance Engines for Calibre xRC
- Mentor Graphics' Calibre Ready for OASIS Stream File Format
- NEC Adopts Synopsys' Proteus OPC Software for 90nm Production
- Magma, ChipX Unify RTL-to-GDSII Design Flow for Structured ASIC Platforms
- Mentor Graphics Adds Xilinx Virtex-4 FPGAs Support to Synthesis Tools
- eSilicon Tapes Out .18-micron SoC Design with Magma's Blast Tools
- SiWorks Standardizes on Blast Create for IP Solutions
- Denali Software Showcases Technology at Intel Developer Forum
- Fujitsu Standardizes on Cadence Incisive Conformal Technology
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