IC Tools News
- Cadence Enables Sequans to Achieve Quick Tapeout of Wireless Broadband Chip
- Accent, ARM and Cadence Validate Low-Power Design Techniques
- Canon Adopts Cadence Encounter RTL Compiler for ASIC Designs
- Epson Doubles Productivity in Chip Tapeout with Encounter RTL Compiler
- Tadiran Adopts Celoxica DK Design Suite for C-based Design and Synthesis
- Cadence Encounter RTL Compiler Reduces Synthesizable Area for Essence
- Cadence Encounter RTL Compiler Speeds Image Processor Tapeout for Nethra
- ATI and TSMC Win X Initiative's Design-to-Manufacturing Catalyst Award
- Cadence Reveals Enterprise Verification Process Automation Strategy
- Cadence Ports Encounter Design Platform to 64-Bit Intel Xeon Processor
- Cadence Accelerates 65nm Design by Supporting TSMC Reference Flow 6.0
- Cadence Enables Oki to Develop Analogue Blocks Five Times Faster
- Giga Scale Develops World's First IC Economic Analysis Engine
- TransEDA Unveils Assertain Verification Closure Management Tool
- Cadence, IBM, and Chartered to Enable 90-nanometer Design Success
- Verum Enables Philips to Reduce Software Defects by Factor of Ten
- Golden Gate Technology Launches Nanometer IC Power Reduction Software
- EVE Adds Capabilities to ZeBu Hardware-Assisted Verification Platform
- Cadence and Faraday Collaborate on Nanometer Design Library
- Cadence Encounter RTL Compiler Enables Ricoh to Tape Out 90nm Chip Early
- Giga Scale IC's InCyte Enables Early Silicon Estimation for DongbuAnam
- Designers Download Giga Scale IC's InCyte Chip Estimation Software
- Accent Selects Giga Scale IC's InCyte for Early Chip Estimation
- Nuelight to Open IC Design Center for OLED Displays in Hyderabad
- Giga Scale IC's InCyte Enables Early Chip Estimation for Accent
- Cadence Incisive Formal Verifier Extends Formal Analysis to Desktops
- TransEDA Debuts imPROVE-HPK AXI Automatic Verification for AMBA AXI
- Calypto Rolls Out SLEC Sequential Logic Equivalence Checking Solution
- Cadence Design Systems Completes Acquisition of Verisity
- Cadence Contributes Schematic Symbol Set to OpenKit Initiative
- Silicon Design Chain Reduces Power of 90-Nanometer Design by 40%
- Cadence Delivers Complex Nanometer Design Capabilities to Wipro
- Customers Ratify Cadence Encounter CeltIC NDC for Low-Power Designs
- Yogitech's OCP eVC Integrates with Magillem Platform Design Environment
- Cadence, Virage Logic to Deliver Timing and Signal Integrity Views
- GUC Successfully Encounters 7 Nanometer Designs with Cadence Technology
- Cadence Designer Network Bolsters Exchange of Ideas and Information
- S3 Succeeds with Cadence Encounter Digital IC Design Platform
- Cadence Palladium II Verifies ATI Technologies' Advanced DTV Chips
- Cadence, IBM, Rising Enable Leading-Edge SCDMA/GSM RF IC Transceiver
- Cadence Wins IEC DesignVision Award for First Encounter GPS Technology
- Sanyo Creates Digital Consumer Product with Cadence Encounter RTL Compiler
- Cadence Encounter Leads Fujitsu to 66 Consecutive Successful Designs
- Cadence Rolls Out Encounter Conformal Constraint Designer
- Cadence Gains Verification Solution and Expertise by Acquiring Verisity
- Sequence Demonstrates Low-Power Design Tools at VLSI Design Conference
- Artisan Standardizes on Synopsys' ESP Full-Custom Memory Verification
- Oki Tapes Out µPLAT with New Cadence Synthesis Low-power Technology
- Winbond Achieves First Pass Success with Synopsys Galaxy Design Platform
- Toshiba SOC, ASIC Customers Flow with Cadence Encounter RTL Compiler
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