IC Tools News
- Magma to Distribute TSMC Libraries for Advanced System-on-Chip Design
- Synopsys Addresses Multi-Standard Verification of Chips With Flexible Telecom Workbench
- Magma Further Accelerates RTL-to-Silicon Flow With New Blast Fusion APX
- Synopsys Announces Growing Industry Support for OpenVera Assertions
- Acer and Cadence Announce Strategic Alliance to Cultivate World-Class Talents in Analog IC Design
- Magma Appoints One Pass Solutions as Distributor in China
- Cadence Completes Purchase of Antrim Assets
- ASE Establishes Cadence Design Flow to Provide High-Performance IC Packaging Solutions
- ICT Solutions Joins Corelis’ Value Added Partner (VAP) program
- Avnet Cilicon Adds Synopsys' FPGA Solution to Avalon Reference Design System
- Physical Synthesis Customers NEC and AMCC Adopt Cadence NanoRoute Ultra for Nanometer Design
- TSMC and Cadence Collaborate to Solve Nanometer Design Challenge on Signal Integrity Closure
- Fujitsu Deploys Cadence Nanometer Analysis Technology to Achieve Timing Closure for High-end Asic Designs
- Artisan Components and Cadence Team to Manage Nanometer Design Risk
- 0-In Delivers CheckerWare Monitors for Leading Interface Standards
- X-FAB Adds Support for Mentor Graphics Calibre and xCalibre
- Magma and IBM Collaborate to Accelerate Chip Designs from Concept to Silicon
- Mentor Graphics Announces ADAPT Partnership Program to Expand Portfolio of Web-Based Component Information
- TSMC and Synopsys Collaborate to Address Signal Integrity Closure Issues
- Texas Instruments Uses Blast Fusion to Deliver 5.5-million-gate ASIC
- Synopsys and OCP-IP Members Jointly Develop SystemC Modeling Methodology
- Synopsys Advances EDA Tool Interoperability with Open Power Format and OpenVera Parser
- Synopsys Adds Noise Modeling Capabilities to Liberty Open Library Standard
- Magma's Integrated RTL-to-GDSII System Adopted by Xellink Communications for High-Speed, High-Capacity Networking Chips
- Magma Expands Presence in Asia With Office in Korea
- Xilinx and Agilent Technologies Deliver Combined Solution to Cut Cost and Time of Programmable In-Circuit System Design
- Exar Teams with Sequence on Comms IC Excellence
- STMicroelectronics Selects Calibre Interactive for Cell and Block Verification
- Synopsys Introduces New Logic BIST Capability to Significantly Reduce Test Cost
- Mentor Graphics Aids in Rapid Adoption of GDSII Replacement Format
- Cadence, IBM Team to Simplify Chip Design Process
- X Initiative Members Deliver First 130 Nanometer X Architecture Masks
- Fujitsu Standardizes on Mentor Graphics Resolution Enhancement Technology Solutions
- Austriamicrosystems Selects Cadence for Analog/Mixed-Signal Design Support
- Synopsys Professional Services Helps Accelerate Implementation of ARCtangent-Based Systems-On-Chips
- Cadence Introduces Single-Architecture Encounter System for Nanometer Design
- Mentor Graphics Announces Design-for-Test Support for Artisan Components' Embedded Memories
- Synopsys Introduces TetraMAX TenX
- Paxonet Communications Uses Magma System to Tape Out Multimillion Gate Networking Traffic Management Device
- Synopsys Teams With TSMC For 90 Nanometer Technology
- Sunplus Picks Celestry for High Performance Clock Tree Synthesis
- Synopsys’ VERA Speeds Verification of SONET/SDH Chip at NEC
- HCL Technologies Adopts Magma Solutions to Extend Physical Design Service Capabilities
- SOTA Selects Celestry for Silicon Accurate Sign-off
- Magma Releases Preliminary Fusion User Group Conference Agenda
- Cadence First Encounter Adopted by Silicon Integrated Systems (SiS) For High Performance Graphics Chip Designs
- 0-In Announces CheckerWare Library and Monitors with Sugar Support
- Mentor Graphics Announces Calibre xRC, Full-chip, Transistor-level Parasitic Extraction for SoC Designs
- Mentor Graphics Announces New Front-to-Back IC Design Flow to Meet Today's Analog/Mixed-Signal SoC Design Challenges
- Rajeev Madhavan of Magma Selected as Top Innovator by Red Herring Magazine
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