ASIC News
- Artesyn Launches High Current Density RoHS Point-of-Load Converters
- Microchip Debuts High-Efficiency, Low-Power Charge Pump DC/DC Converters
- NEC Creates Signal-Reshaping LSI for 40 Gbps Optical Fiber Transmission
- Inphi Unveils Linear Transimpedance Amplifier with Automatic Gain Control
- Microchip Creates Low-power, 6-bit, Volatile Digital Potentiometers
- Summit Sets Records with Digitally Programmable Li-Ion Charger IC
- Microchip Debuts TC4451, TC4452 High-Current, High-Speed MOSFET Drivers
- Anchor Bay Rolls Out Chip and System Level Video Processing Solutions
- Microchip Introduces MCP3550 Low-Pow, 22-Bit Delta-Sigma A/D Converters
- SIDSA Rolls Out LOREN DVB-H Demodulator Chip for Mobile TV Services
- Sensory Adds Interactive and Robotic Features to Speech Recognition IC
- Acoustic Technologies Unveils ATH3100 Full-Duplex Voice Processing IC
- DSP Optimization Takes Off with AccelChip's IP-Explorer Technology
- CoreSim Replaces Obsolete ASIC with Board Powered by LatticeEC FPGA
- Fujitsu to Ship New Structured ASIC Built Using Cadence Encounter
- Talijon Engineering Replaces Obsolete ASIC with LatticeEC FPGA
- Xilinx and CMC Sponsor International Conference on VLSI Design
- Altera Defines the SoC Methodology at Denali MemCon
- BAE Creates Radiation-Hardened Space-Qualified ASICs with Synopsys' Galaxy
- Altera to Discuss Selecting Best ASIC Solutions in Web Seminar
- Magma, ChipX Unify RTL-to-GDSII Design Flow for Structured ASIC Platforms
- Agilent Breaks Performance Record with Embedded SerDes ASIC
- Agilent Rolls Out 400 Million ASICs for Imaging Applications
- Synplicity Rolls Out Synplify ASIC Synthesis Tool for NEC Gate Arrays
- Altera Discusses Current Design Alternatives at DAC
- Cadence Encounter Supports Virage Logic Structured-ASIC Design Libraries
- Siemens Selects Mentor's Catapult C Synthesis for RTL Implementation
- Catapult C Synthesis Creates RTL from Untimed C++ 20 Times Faster
- Magma, Faraday Unveil RTL-to-GDSII Flow for Structured ASIC Platforms
- Magma Supports Virage Logic Structured ASIC Design Libraries
- IBM Sublicenses Denali's Databahn DDR Controller IP Cores
- Synplicity Enhances Certify Prototyping Software for Large ASICs
- Magma Characterizes BAE Systems Radiation-hardened ASIC Libraries
- Agilent Offers ASIC and System Design Services with SoC Design Center
- Agere ASIC Centers Support Cadence Encounter RTL Compiler Synthesis
- TAK'ASIC Offers Higher Price/Performance with TAKB4 Processor
- NI GPIB Products Increases Throughput with IEEE 488.1-2003 Standard
- Adaptec Rolls Out ASIC for Serial Attached SCSI Controller
- Customers Mix and Match with Virage Logic Powered Kawasaki's Matrix
- Altera Discusses ASIC and FPGA Design Flow Synergy at SNUG
- Cadence Encounter RTL Compiler Synthesis Rolls into Agere's ASIC Centers
- Oki Unveils Fully Qualified Wafer-level Chip Scale Package for ASIC
- Altera HardCopy Enables Motorola to Speed Development of Horizon BTS
- Atmel Develops Chip to Provide MP3 Player Manufacturers More Functionality
- Kawasaki Expands ASIC IP Portfolio with ARC’s Processor Technology
- Power Management IC Customization is Most Important Factor for OEMs
- Peerless Targets Color Tandem MFPs with QuickPrint Xtreme 1100 ASIC
- TI Develops Interleaved PWM Controllers on Single Chip
- Conexant Supports Windows XP Media Center 2004 with Chipsets
- Mentor Gets Formal with Scalable Verification for Largest ASIC Designs
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