Verilog, VHDL, other HDL News
- TransEDA Adds PSL Support to Assertain Verification Closure Solution
- Temento Adds System Verilog Assertions Support to DiaLite Platform
- TransEDA Releases Assertain Next Generation Verification Closure Solution
- Carbon Design Systems Breaks Down ESL Adoption Barriers with SOC-VSP
- SystemCrafter, Orange Tree Debut Low-Cost SystemC Synthesis Tool v2
- Summit Design Strengthens Visual Elite for HDL and ESL Designers
- SystemCrafter, Orange Tree Receive Ultimate Award for SystemC Synthesis
- Cadence's Incisive Design Team Enables SystemVerilog from Plan to Closure
- Cadence Design Systems Accelerates IEEE P1647 e Standardization
- Aldec Licenses 10,000 Riviera HDL Simulators to Renesas Design Vietnam Co
- Cadence Enhances SystemVerilog Usability with Donation to IEEE
- TransEDA Enhances Coverage Accuracy with Expression Coverability
- Aldec Rolls Out Active-HDL 6.3, Altera Edition
- TransEDA's Verification Navigator Tool Suite Supports SystemVerilog
- Lattice Rolls Out ispLEVER-Starter 4.2 Programmable Logic Design Tools
- Orange Tree, SystemCrafter Introduce SystemCrafter Package for SystemC
- Aldec Introduces Active-HDL 6.3, Actel Edition
- CADinformatique Distributes Mentor's HDL Simulation and Synthesis Tools
- Aldec and Magma Create Design Flow Interface for Active-HDL, PALACE
- Aldec Wins Best Value Award for Easy-to-Use Active-HDL Simulator
- CoWare, AccelChip Team for Design and Verification Flow for MATLAB
- Carbon Design Integrates DesignPlayer with Virtutech's Simics ISS
- Calibre and ModelSim Support 64-Bit Linux - AMD64 Processor Platforms
- Denali Supports Synopsys SystemVerilog Catalyst Program
- 0-In's Archer Verification System Supports SystemVerilog and VHDL
- Magma Joins Accellera to Focus on EDA Standards
- Industry Leaders Form SystemVerilog Implementation Working Group
- ASIC Group Offers 50+ Tips for Creating Better Verilog Designs
- Synopsys Joins IEEE Standards Association as Corporate Member
- Cadence Supports VHDL with Encounter RTL Compiler Ultra Synthesis Tool
- ARM, Synopsys Develop Reference Methodology with SystemVerilog
- Mentor Supports SystemVerilog and SystemC with ADVance MSTM 4.0
- SystemVerilog NOW! Seminars Move to Israel, Germany, UK and Japan
- Agilent Targets RFIC and MMIC Designers with Verilog-A Support
- Aldec and Celoxica Combine Products to Create Mixed HDL and C-Language
- MathWorks, Mentor Provide System Co-Simulation with Link for ModelSim
- Mentor Graphics Unveils Scalable Verification Platform to Bridge Gap
- Cadence Unifies Language Standards by Supporting SystemVerilog
- Industry Leaders Offer SystemVerilog NOW! Technical Seminars
- ARTiSAN's Real-time Studio Pro in Control at Goodrich Engine Systems
- Agilent EDA Tools to Support Tiburon Verilog-A Modeling Technology
- Mentor Addresses Critical Design Creation with HDL Designer Series
- Cadence Openly Donates Verilog Language Extensions to IEEE
- SanDisk Attacks Multi-level Cell NAND Design-in with Shark Tool Kit
- Mentor Graphics, STMicroelectronics Target AMS and RF Designers
- Synopsys VCS HDL Simulator Supports AMD Opteron Processor on Linux
- Updated ModelSim from Mentor Offers Improved Simulation Performance
- Mentor Graphics, Thales, Xilinx to Develop FPGA Formal Verification Solution
- TI Choses Cadence First Encounter for Physical Prototype and Placement System
- Mentor Graphics Offers 70 Percent Savings on New Training Package for HDL Design Tools
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