Verilog, VHDL, other HDL News
- Model Technology's ModelSim Achieves Verilog/Mixed HDL Sign-Off at austriamicrosystems
- TTChip Increases IP Design Productivity with Mentor Graphics Design Tools
- Synopsys Acquires Co-Design Automation
- Nec Electronics Singapore Adopts Celoxica DK1 Design Suite For Next Generation Chip Design
- 0-In Announces CheckerWare Library and Monitors with Sugar Support
- Mentor Graphics Provides Tools in New Programmable Logic Designers Verilog Training Program
- Mentor Graphics Adds New Design Creation and Management Features for Complex FPGA Design in FPGA Advantage 5.3
- Cypress Quantum38K™ CPLDs Add Mentor Graphics Design Support
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