Configurable Application-Specific Signal Processors Speed Design and Development
COST-EFFICIENT FLEXIBILITY
The cost of a DSP depends heavily on its on-chip memory size and clock speed. Getting the most bang for your buck has always been the name of the game. With limited resources, how can we offer flexibility without, at times, wasting valuable resources?
Let's assume that we include all the features that we've identified. Let's also assume that we support all possible types of interfaces (HPI, PCI, TDM, Ethernet). Each feature requires program memory and per-channel data memory, so the chip needs a considerable amount of memory. If we want to maintain as much flexibility as possible, we should use a DSP that not only includes a large on-chip memory, but also operates at a high clock speed to maximize the number of channels it can support.
What we end up with is a chip that is flexible enough for most conferencing applications but is most likely too expensive for all but the high-end applications.
BUILD TIME VS. RUN TIME
Again, how can we offer flexibility without wasting valuable resources? One answer is to rely on build-time configuration. The principles are simple: If you don't need a feature, don't include it in the software image. If you don't need to use a peripheral, don't include support for it in the software image.
The build-time versus run-time trade-off extends beyond feature sets into several considerations: memory allocation and management, CPU utilization, peripheral configuration, system configuration, and channel configuration.
Thus, given the number of possible features, peripherals, and DSP chips in a DSP family, such as Texas Instruments' TMS320C6000 DSP platform, the number of combinations for build-time configuration is staggering. It looks as if we've created a configuration management nightmare. Fortunately, CAD techniques will save us.
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