Verification of Mixed-Signal Systems

CONCLUSION

A standard and consolidated methodology and a common environment for the verification of mixed-signal system are not available yet: analogue/digital design and simulation activities are only linked at top-level and for smaller sub-systems. This is due to the fact that analogue simulators are orders of magnitude slower than digital simulators [4]. The end effect is that even trivial design mistakes are enough to cause serious failures of the whole system, because the users can forget to verify a particular case by using traditional test-benches. Moreover, many hypotheses have to be assumed on the analogue/digital interface.

It is proven [6] that by using AHDL models, the simulations are very fast and can be very accurate if the non ideal effects are modelled in a proper way [5]. Based on that, the integrated mixed-signal verification environment proposed in this paper is an answer to the previous mentioned open issues: for instance, it can both randomise the analogue sub-system non ideal effects as in a classical fully analogue transistor level simulation approach, and also produce a coverage analysis based on covered input/output spaces and analogue/digital coverage items as well.

In brief, this approach links analogue and digital worlds in a common environment to help the verification engineer to produce more test cases than in traditional approaches, in a faster way, minimizing overlap simulation and in a virtually independent way from the designer point of view. Moreover, it provides ready to use verification kit and verification components to improve productivity and reliability.

REFERENCES

[1] M.Edwards, W.Rosenstiel, M.Witerholer, T.Oppold, C.Schilz-Key, Y.Kashai, T.Kuhn, "Object Oriented Hardware Synthesis and Verification", Proc. of the 14th International Symposium on System Synthesis, 2001, Montreal, Canada, pp. 189-194
[2] Bill Luo, Jim Lear, "A Unified Functional Verification Approach for Mixed Analog-Digital ASIC Designs", Legerty INC, DesignCon 2003
[3] Koji Ara, Kei Suzuki, Hitachi, Ltd, "A Proposal for Transaction-Level Verification with Component Wrapper Language", Proc. of Design Automation and Test in Europe (DATE), March 03-07 2003, Munich, Germany
[4] C.Brown, "Mastering of Mixed-Signal Verification" EETIMES, 17 March, 2004
[5] A.J. Ginés, E. Peralías, A. Rueda, N. Martínez Madrid and R. Seepold, "A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects", Proc. of Design Automation and Test in Europe (DATE), March 2002, Paris, France
[6] E. Peralías, A. J. Acosta, A. Rueda, J. L. Huertas, "A VHDL- based Methodology for the Design and Verification of Pipeline A/D Converters", Proc. of Design Automation and Test in Europe (DATE), March 2000, Paris, France, pp. 534-538
[7] IEEE 1647 web site: www.ieee1647.org
[8] Verilog-AMS Language Reference Manual: "Analog & Mixed-Signal Exstension to Verilog HDL", version 2.1, January 20, 2003
[9] "CAN Specification, version 2.0", Robert Bosch, 1991
[10] A.Di Blasi, F.Colucci, R.Mariani, "Y-CAN Platform: A Re-usable Platform for Design, Verification and Validation of CAN-Based Systems On a Chip", ETS-2003 Symposium, May2003
[11] C.Turner, C.Mueller, "Re-usable CAN IP block", CAN newsletter 3/2002 CIA
[12] eVC CAN datasheet, YOGITECH SpA, 2002
[13] R.Mariani, M.Chiavacci, G.Bonfini "Foundamentals of a novel approach for mixed analogue-digital verification", 9th IEEE European Test Symposium, Informal Session, Ajaccio (Corsica), 23-26 May 2004
[14] G.Bonfini, M.Chiavacci, F.Colucci, F.Gronchi, R.Mariani, E.Pescari, A.Sterpin, "Fault Coverage in A New Mixed-Signal Verification Approach", International Mixed-Signals Testing Workshop 2005 (IMSTW'05), 27-29 June, Cannes, France.
[15] "e Reuse Methodology (eRM) Developer Manual Version 4.3.5"

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