Verification of Mixed-Signal Systems
MIXED-SIGNAL VERIFICATION APPROACH
General Concept The mixed-signal verification approach proposed by YOGITECH combines digital and analogue verification, providing verification engineers with a methodology and a set of IPs to interface Specman with mixed-signal multi languages simulators. In such approach, analogue stimuli and output metrics can be controlled by the SpecMan environment, allowing a top-level control of the verification process together with a comprehensive methodology to verify the effect of behavioural models on the whole system.
Figure 2: The Integrated Mixed Signal Verification Environment
A schematic representation of a mixed verification environment is shown in Figure 2. The interface between analogue and digital domains is managed by verification terminal called vSource or vProbes (Figure 3) that act as extended drivers (or, more precisely, Bus Functional Models as named in the eRM standard [15]) and extended monitors. The digital signals, representing a high level description of the analogue information, are transferred by those terminals to the verification environment developed in "e" language. It includes scoreboards, checkers, sequence and virtual sequence generators that are normally part of the dynamic functional verification of digital circuits. Moreover, the coverage analysis layer is part of such environment as well.
Figure 3: vSource and vProbe
The verification terminals are mixed-signal blocks, including a part described in AHDL (for instance VerilogAMS [8]) and a part written in "e" language. For each terminal, the configuration set defines its features and Specman statically sets it. The parameter set defines analogue signals parameters and it is dynamically driven according to verification plan constraints.
An important feature presented both in vSources and vProbes is the time manager. In fact, the interaction between mixed-signal simulators and Specman environment is time consuming and it should be implemented only when it really needs to. As strategic guideline, this task is delocalized in order to optimize the efficiency and it is performed directly by the interface elements.
In the proposed methodology, the time required for the environment building: before starting the verification phase running simulations and discovering bugs can be significant because it is necessary to set up all the necessary structures. This also happens in the dynamic functional verification for digital circuit where the use of off-the-shelf verification components is the other key point to drastically reduce time to first test, increasing verification team productivity and improve system's quality: the verification team has more time to focus on most problematic DUT aspects and the need in the team of outstanding application knowledge is also less mandatory. Verification components (called eVCs, e-Verification components, in case they are developed using Cadence's e-language) can be plugged in the environment and, based on that, upper-level verification sequences can be built much easily.
The same concept is applicable to the mixed-signal verification (Figure 4): Mixed-Signal Verification Components include a set of vTerminals, procedures in "e" code elaborating info coming to/from verification terminals and a verification environment with instantiation, top level definition; virtual sequence driver for sequences synchronization and a test suite can be developed and re-used whenever necessary.
Figure 4: Time Requirements for Yogitech's Mixed Signal Verification
However, to be really effective, verification components should have the best quality: they are not just a piece of software running on an EDA tool. They should be built by teams with a deep knowledge of mixed-signal verification and high level modelling of physical events, based on a detailed verification plan, following precise re-use methodologies (such as eRM e Reuse Methodology, defined by Cadence) and quickly following the changes of verification tools.
MIXED-SIGNAL VERIFICATION KIT
According to the previous paragraph, in order to significantly reduce the time and effort needed to set up the verification environment and achieve the first results, YOGITECH provides the Mixed-Signal Verification Kit, mostly suitable for top-level verification of a mixed signal design.
The Mixed-Signal Verification Kit consists of:
- Library of mixed-signal verification components for basic analogue blocks (band gap, DC-DC converter, voltage reference, Oscillator, etc)
- Library of verification terminals (vProbes and vSource) suitable to stimulate/monitor a system which includes standard functional blocks such as voltage references generators, DC-DC converters, amplifiers, oscillators, comparators, thermal shut down, power on reset, etc
- Library of "e" components, templates and test cases to elaborate info coming to/from verification terminals such as checkers and sequence drivers connected to the verification terminals, scoreboards to correlate system outputs with expected results, coverage items measuring verification progress
- Verification environment, including config and env structures for components (coming from the two mentioned libraries) instantiation, ports definition and ports binding, top level definition, virtual sequence driver for sequences synchronization
Through the verification environment the user can build what is required by using library components such as bricks.
The Mixed-Signal Verification Kit is eRM compatible1, so it is possible to instantiate different vProbes and vSources and other eVCs without collisions and with a proper synchronisation. It is possible to add ready to use components from the kit and/or to extend the "e" part adding custom elaborations (white blocks in the pictures).
1 The extension of the eRM to mixed-signal verification is under development.
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