Verification of Mixed-Signal Systems
DESIGN AND VERIFICATION CONCEPTS
In the design phase (Figure 1), the design team, starting from the specification, defines the architecture of the circuit (it can be an analogue block or a digital system), defines each component and its interaction and proceeds with intensive simulations evaluating the performances and stressing the circuit toward its limit taking into account different environment's conditions (temperature, power supply, inputs, loads, etc). Here, this process is called characterization. For instance, for an operational amplifier, the designer will simulate an input dynamic range slightly larger than the one stated in the specification in order to be sure to have "enough" margin; he always calculated gain and phase margins and simulates carefully those parameters in all possible conditions related to the circuit (e.g. process parameters) and to the external conditions (e.g. power supply) even if they are not directly mentioned in the specifications; the same for step response and so on. In digital design, this process is more automated by the use of different kind of formal checks for high level description code, detailed analysis of synthesis results and static time analysis.
Figure 1: Design and Verification Phase
In addition to the specification, the verification phase (Figure 1) has an input to the circuit. The purpose of the verification phase is to verify if the circuit itself is compliant with the specification set. In principle, things not specified should not be verified because the behaviour of the circuit in those conditions is simply unknown. Of course, normally the process is interactive in the sense that verification is also used to patch holes in spec. In this phase, the verification team will perform intensive simulations and this process is called validation. The circuit to be verified is called instead Device Under Test.
The dynamic verification for digital circuit is based on state-of-the art methodologies and tools, based on object oriented programming, stimuli generation using values randomization and constrained approach, coverage definition and calculation, which almost completely replaced the old approach based on HDL test-benches with high level tasks and procedures.
Specman Elite® (by Cadence Design System, www.cadence.com/verisity) is a very powerful tool for automating the process of functional verification. Specman offers a comprehensive environment for all aspects of the verification flow: automatic generation of functional tests, data and temporal checking, functional coverage analysis, and HDL (High-Description Language) simulation control. Specman includes a powerful verification language as well, called "e" (under standardization with the IEEE initiative P1647 [7]), that allows the verification engineer to capture the rules from specifications as well as generate tests automatically.
On the other hand, for analog circuit, the circuit's characterization often replaces the validation phase, increasing the effort due to the larger amount of simulations to be done without enough advantages in terms of reliability and bug discovery: the use of a means not thought on purpose makes the process inefficient and time consuming.
Normally verification of an analogue block consists of some steps that as described below.
- Environment set up where, based on the functionality to be verified the DUT or part of it (the one that only affect that functionality) together with the necessary external components (e.g. loads) are instantiated in a test-bench often in a graphical mode; Sensitive parameters are then identified and considered in the simulation set up; then, the stimuli needed to excite that functionality are defined and included in the test-bench; it is worth to note that those stimuli normally cannot be influenced by simulation results setting a sort of open loop process.
- Simulations covering all the defined scenarios depending on input stimuli, parameters and output signals.
- The results collection and analysis is often based on the extracted information from waveform, but a visual analysis of signal behaviour is time consuming and does not allow re-usability (i.e. each time the process starts again); there are no real methods to evaluate the verification progress; normally there is not a verification plan clearly written or metrics to evaluate the coverage of the input/output space.
A detailed knowledge of the circuit and of the application is mandatory to be able to reach a good level of verification, whatever "good level" means considering the lack of metrics. In brief, designer's experience and knowledge are the key points for verification of analogue blocks.
Things are not better for mixed signal circuits that inherit the problems of the analogue side and reduce the effectiveness of the digital approach with, on top, the risk to double the effort without improving the results. In fact, there are normally two completely separated environments for digital and analogue top-level verification.
From a digital side, dummy models described in HDL (Verilog, VHDL or C) for involved analogue blocks are used. But these models are developed on purpose and therefore it often happens that they do not take into account all the interesting effects and it is very complex to compare them with the "real" circuit coming from design phase. Due to that, the interface between analogue and digital parts is under-estimated or overlooked.
Real mix-mode simulations involving analogue and digital circuits are performed in the analogue side (e.g. analogue engineers take care of them) and so they inherit all the limits of analogue verification:
- Stimuli defined at a very low abstraction level
- Results collection mainly based on waveforms analysis
- Corner cases evaluation often based only on designer's experiences
- Stimuli generation cannot be influenced by simulation results (open loop process)
A more integrated, automated and re-usable approach is strongly needed for verification of mixed signal circuits — an approach that creates a unique environment in which a verification engineer without a deep knowledge of design and application can validate the circuit.
Moreover, such solution should include also close loop capability, i.e. stimuli to be applied to the DUT can be influenced by simulation results.
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