By: G.Bonfini, M. Chiavacci, R. Mariani, E. Pescari
YOGITECH SPA, via Lenin 132/p, 56017 San Martino Ulmiano (Pisa), Italia
Electric and Electronic systems account for 49.2% of registered breakdowns (source: Allgemeiner Deutscher Automobil Club, 2003). Recent statistics on ICs indicate that 71% of System-on-Chip (SoC) re-spins are due to functional bugs, and 47% of them are due to incorrect or incomplete specifications. Moreover, 14% of failing SoCs have bugs in reused components or IPs. This is why 60-70% of the entire product cycle for a complex chip is dedicated to verification tasks.
But real systems are in fact mixed-signal and here, functional verification always requires the interaction between the different methodologies needed to verify the digital elements and the analogue ones.
YOGITECH's proposed approach combines digital and analogue verification, providing verification engineers with a methodology and a set of intellectual properties to interface Specman Elite with a mixed-signal (multi language) simulator that results in a mixed signal verification environment able to manage high level models and spice level net-list.
Due to the complex interaction between analogue and digital verification methodologies , the overall verification coverage of a mixed-signal system is very often decreased and system bugs appear very late in the design process. Verification of digital sub-systems is based on advanced techniques (, ), such as constraints capture, randomised or pseudo-randomised stimulus-generation, and result collection with coverage analysis. On the other side, the verification of analogue sub-systems is based on classical approaches and are often limited to very basic functionalities.
Mixed-signal simulation tools available in the market allows the simulations of both analogue and digital blocks in the same test-bench. Moreover, the whole circuit is slit in mixed subsystems in order to verify a specific function of the whole device (i.e. reset and start-up conditions, power down/up signals polarity, functionality of analogue block selected and/or driven by digital part, test-modes). This approach reduces the complexity of the simulations (mainly in terms of run time), but it often happens that not all the interactions between different blocks are considered and the consequent lack of coverage does not allow discovering bugs, which appears instead during silicon testing. The information extracted from these multiple mix-mode simulations depends on stimuli generation and results collection strategies often based only on the designer's experiences without a clear methodology and documentation.
YOGITECH's proposed approach (, ) extends to mixed-signal circuits the most advanced techniques for dynamic functional verification and allows the development of off-the-shelf verification mixed-signal components that drastically reduce the time to first test, increasing verification team productivity and improving design quality.
In such scenario, both analogue stimuli and output metrics can be generated in the common environment, allowing a top-level control of the verification process by a set of intellectual properties able to interface the analogue domain: the verification sources (vSources) to generate analogue signals controlled by digital parameters and the verification probes (vProbes) to elaborate and transfer analogue signals from the mixed-domain simulator to the digital verification environment.
A brief introduction on standard methodology for digital, analogue and mixed-signal verification is described in the next section. Then, the third section describes the proposed approach and the Mixed-Signal Verification Kit, which provides the necessary bricks to build a complex mixed-signal verification environment.
As proof-of-concept, some benchmarks are described pages four and five. The conclusions are then highlighted in the last section.
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